Added PC histogram option.

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index 2bc69f0d76b53f73dc15752eca92814fc5ea94bb..9e1362e08343ad5fa20a71abe5b59e31102b118d 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -19,33 +19,37 @@ public:
   ~sim_t();
 
   // run the simulation to completion
-  void run();
+  int run();
   bool running();
   void stop();
-  void set_debug(bool value) { debug = value; }
+  void set_debug(bool value);
+  void set_histogram(bool value);
+  void set_procs_debug(bool value);
+  htif_isasim_t* get_htif() { return htif.get(); }
 
   // deliver an IPI to a specific processor
   void send_ipi(reg_t who);
 
   // returns the number of processors in this simulator
   size_t num_cores() { return procs.size(); }
-  processor_t* get_core(size_t i) { return procs[i]; }
+  processor_t* get_core(size_t i) { return procs.at(i); }
 
   // read one of the system control registers
   reg_t get_scr(int which);
 
 private:
-  std::auto_ptr<htif_isasim_t> htif;
+  std::unique_ptr<htif_isasim_t> htif;
   char* mem; // main memory
   size_t memsz; // memory size in bytes
-  mmu_t* mmu; // debug port into main memory
+  mmu_t* debug_mmu;  // debug port into main memory
   std::vector<processor_t*> procs;
 
-  void step(size_t n, bool noisy); // step through simulation
-  static const size_t INTERLEAVE = 1000;
+  void step(size_t n); // step through simulation
+  static const size_t INTERLEAVE = 5000;
   size_t current_step;
   size_t current_proc;
   bool debug;
+  bool histogram_enabled; // provide a histogram of PCs
 
   // presents a prompt for introspection into the simulation
   void interactive();
@@ -70,4 +74,6 @@ private:
   friend class htif_isasim_t;
 };
 
+extern volatile bool ctrlc_pressed;
+
 #endif