git.libre-soc.org Git - riscv-tests.git/history

2018-10-16	Luke Kenneth Casso...	modified VL and MVL CSRs to range from 1-XLEN rather...	tree \| commitdiff
2018-10-09	Luke Kenneth Casso...	alter unit tests to match change in CSR table format	tree \| commitdiff
2018-10-02	Luke Kenneth Casso...	actually sv vector-vector add worked fine	tree \| commitdiff
2018-10-02	Luke Kenneth Casso...	add rv64ud sv fadd test, shows flaw in loop for 3-arg...	tree \| commitdiff
2017-11-27	Torbjørn	Rv32ud tests (#108)	tree \| commitdiff
2017-05-25	Palmer Dabbelt	Merge pull request #53 from richardxia/fail-if-simulato...	tree \| commitdiff
2017-05-22	Andrew Waterman	minNum -> minimumNumber	tree \| commitdiff
2017-04-17	Megan Wachs	Merge remote-tracking branch 'origin/priv-1.10' into...	tree \| commitdiff
2017-04-11	Andrew Waterman	Improve fp ldst/move tests; remove redundant fsgnj...	tree \| commitdiff
2017-03-21	Andrew Waterman	Avoid x3 (gp), which is now TESTNUM	tree \| commitdiff
2017-02-02	Andrew Waterman	Use NaN macros	tree \| commitdiff
2017-02-02	Andrew Waterman	Test FMIN/FMAX NaN behavior	tree \| commitdiff
2017-02-01	Andrew Waterman	Test qNaN and sNaN inputs to FP comparisons	tree \| commitdiff
2016-08-12	Tim Newsome	Merge pull request #21 from sifive/add_freedom_sim_targets	tree \| commitdiff
2016-08-08	Colin Schmidt	move fclass macros into the same file as the rest ...	tree \| commitdiff
2016-06-22	Howard Mao	split up rv64uf and rv64ud isa tests	tree \| commitdiff