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CLR SV CSRs now clears by popping, TODO make 1 instr
[riscv-tests.git]
/
isa
/
rv64ud
/
2018-11-04
Luke Kenneth Casso...
comments on remap csrs
tree
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commitdiff
2018-11-04
Luke Kenneth Casso...
add shape remap fadd unit test
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commitdiff
2018-10-16
Luke Kenneth Casso...
modified VL and MVL CSRs to range from 1-XLEN rather...
tree
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commitdiff
2018-10-09
Luke Kenneth Casso...
alter unit tests to match change in CSR table format
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commitdiff
2018-10-02
Luke Kenneth Casso...
actually sv vector-vector add worked fine
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commitdiff
2018-10-02
Luke Kenneth Casso...
add rv64ud sv fadd test, shows flaw in loop for 3-arg...
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commitdiff
2017-11-27
Torbjørn
Rv32ud tests (#108)
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commitdiff
2017-05-25
Palmer Dabbelt
Merge pull request #53 from richardxia/fail-if-simulato...
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commitdiff
2017-05-22
Andrew Waterman
minNum -> minimumNumber
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commitdiff
2017-04-17
Megan Wachs
Merge remote-tracking branch 'origin/priv-1.10' into...
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commitdiff
2017-04-11
Andrew Waterman
Improve fp ldst/move tests; remove redundant fsgnj...
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commitdiff
2017-03-21
Andrew Waterman
Avoid x3 (gp), which is now TESTNUM
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commitdiff
2017-02-02
Andrew Waterman
Use NaN macros
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commitdiff
2017-02-02
Andrew Waterman
Test FMIN/FMAX NaN behavior
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commitdiff
2017-02-01
Andrew Waterman
Test qNaN and sNaN inputs to FP comparisons
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commitdiff
2016-08-12
Tim Newsome
Merge pull request #21 from sifive/add_freedom_sim_targets
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commitdiff
2016-08-08
Colin Schmidt
move fclass macros into the same file as the rest ...
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commitdiff
2016-06-22
Howard Mao
split up rv64uf and rv64ud isa tests
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commitdiff