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Added PC histogram option.
[riscv-isa-sim.git]
/
riscv
/
encoding.h
2014-04-03
Stephen Twigg
Merge branch 'tm'
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2014-04-03
Stephen Twigg
Sync encoding in opcodes
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2014-03-18
Andrew Waterman
Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
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2014-03-12
Andrew Waterman
New FP encoding
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2014-03-07
Andrew Waterman
Add fclass.{s|d} instructions
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2014-02-15
Andrew Waterman
Renumber uarch CSRs into custom CSR space
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2014-02-06
Yunsup Lee
commit missing definitions for uarch counters
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2014-01-22
Andrew Waterman
Use auto-generated trap cause numbers
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-12-09
Andrew Waterman
New RDCYCLE encoding
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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