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Add --disable-dtb option to suppress writing the DTB to memory
[riscv-isa-sim.git]
/
riscv
/
insns
/
csrrsi.h
2018-03-08
Tim Newsome
Merge pull request #177 from riscv/debug_auth
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2018-03-03
Andrew Waterman
Implement clearing-misa.C-while-PC-is-misaligned proposal
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2016-05-21
Andy Wright
Some bugfixes for CSR reading and setting FS for fflags...
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2015-02-08
Andrew Waterman
Use xlen, not xprlen, to refer to x-register width
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2014-12-01
Andrew Waterman
Implement timer faithfully
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2014-04-03
Stephen Twigg
Merge branch 'tm'
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2014-03-18
Andrew Waterman
Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2013-12-09
Andrew Waterman
New RDCYCLE encoding
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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