git.libre-soc.org Git - riscv-isa-sim.git/history

2011-01-19	Andrew Waterman	[opcodes, sim, xcc] made *w insns illegal in RV32	blob \| commitdiff \| raw
2010-11-22	Andrew Waterman	[pk] various PK cleanups/speedups	blob \| commitdiff \| raw \| diff to current
2010-11-22	Andrew Waterman	[xcc, sim, pk, opcodes] new instruction encoding!	blob \| commitdiff \| raw \| diff to current
2010-10-26	Andrew Waterman	[sim] removed unnecessary trap in mfcr instruction	blob \| commitdiff \| raw \| diff to current
2010-10-26	Yunsup Lee	[pk,sim,xcc] get rid of at register, introduce tp register	blob \| commitdiff \| raw \| diff to current
2010-09-21	Andrew Waterman	[xcc, sim] changed instruction format so imm12 subs...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	Merge branch 'master' of /project/eecs/parlab/git/proje...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	[pk, sim] added interrupt support to sim; added timer...	blob \| commitdiff \| raw \| diff to current
2010-09-07	Andrew Waterman	[sim, xcc] bthread threading model exposed; insn encodi...	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike