git.libre-soc.org Git - riscv-isa-sim.git/history

2011-01-19	Andrew Waterman	[opcodes, sim, xcc] made *w insns illegal in RV32	blob \| commitdiff \| raw
2010-11-22	Andrew Waterman	[xcc, sim, pk, opcodes] new instruction encoding!	blob \| commitdiff \| raw \| diff to current
2010-10-03	Andrew Waterman	[xcc, sim] mff now uses rs2 for data	blob \| commitdiff \| raw \| diff to current
2010-09-21	Andrew Waterman	[xcc, sim] changed instruction format so imm12 subs...	blob \| commitdiff \| raw \| diff to current
2010-09-07	Andrew Waterman	[sim, xcc] bthread threading model exposed; insn encodi...	blob \| commitdiff \| raw \| diff to current
2010-08-10	Andrew Waterman	[xcc,sim] implement FP using softfloat	blob \| commitdiff \| raw \| diff to current
2010-08-05	Andrew Waterman	[xcc,pk,sim] Added first part of FP support	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike