git.libre-soc.org Git - riscv-isa-sim.git/history

2011-02-05	Andrew Waterman	[sim,pk] added interrupt-pending field to cause reg	blob \| commitdiff \| raw
2010-10-05	Andrew Waterman	[xcc,sim] eliminated vectored traps	blob \| commitdiff \| raw \| diff to current
2010-09-21	Andrew Waterman	[xcc, sim] changed instruction format so imm12 subs...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	Merge branch 'master' of /project/eecs/parlab/git/proje...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	[pk, sim] added interrupt support to sim; added timer...	blob \| commitdiff \| raw \| diff to current
2010-09-08	Yunsup Lee	[sim] add while to interactive_until	blob \| commitdiff \| raw \| diff to current
2010-09-07	Andrew Waterman	[sim, xcc] added PCRs to replace k0 and k1	blob \| commitdiff \| raw \| diff to current
2010-08-24	Andrew Waterman	[sim] privileged mode support for 32-bit operation	blob \| commitdiff \| raw \| diff to current
2010-08-04	Andrew Waterman	[pk,sim,xcc] Renamed instructions to RISC-V spec	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike