git.libre-soc.org Git - riscv-isa-sim.git/history

2015-03-13	Andrew Waterman	Update to new privileged spec	blob \| commitdiff \| raw
2013-09-27	Andrew Waterman	Use WRITE_RD/WRITE_FRD macros to write registers	blob \| commitdiff \| raw \| diff to current
2011-06-20	Andrew Waterman	temporary undoing of renaming	blob \| commitdiff \| raw \| diff to current
2011-06-13	Andrew Waterman	[sim] renamed to riscv-isa-run	blob \| commitdiff \| raw
2011-01-19	Andrew Waterman	[opcodes, sim, xcc] made *w insns illegal in RV32	blob \| commitdiff \| raw \| diff to current
2010-11-22	Andrew Waterman	[xcc, sim, pk, opcodes] new instruction encoding!	blob \| commitdiff \| raw \| diff to current
2010-09-22	Andrew Waterman	[sim] fixed bug in which shift operands were reversed	blob \| commitdiff \| raw \| diff to current
2010-09-21	Andrew Waterman	[xcc, sim] changed instruction format so imm12 subs...	blob \| commitdiff \| raw \| diff to current
2010-09-13	Andrew Waterman	[sim] renamed sllv to sll (same for other shifts)	blob \| commitdiff \| raw \| diff to current
2010-09-13	Andrew Waterman	[xcc, sim] moved shamt field and renamed shifts	blob \| commitdiff \| raw
2010-08-04	Andrew Waterman	[pk,sim,xcc] Renamed instructions to RISC-V spec	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike