2018-10-04 |
Luke Kenneth Casso... | reorganise twin-predication |
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2018-10-04 |
Luke Kenneth Casso... | big reorganisation to support twin-predication |
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2018-10-03 |
Luke Kenneth Casso... | add in twin-predication identification |
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2018-10-03 |
Luke Kenneth Casso... | decided not to change the behaviour of LOAD/STORE |
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2018-10-02 |
Luke Kenneth Casso... | start work on parallelsing LOAD, pass in parameter... |
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2018-10-02 |
Luke Kenneth Casso... | debug print for floating-point regs |
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2018-10-01 |
Luke Kenneth Casso... | add comment explaining why invert isnt done in zeroing... |
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2018-10-01 |
Luke Kenneth Casso... | add comment explaining use of insn._rd() in zeroing |
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2018-10-01 |
Luke Kenneth Casso... | whoops vloop continuation logic the wrong way round |
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2018-09-30 |
Luke Kenneth Casso... | update template comment |
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2018-09-30 |
Luke Kenneth Casso... | lots of debugging of predication, found other errors |
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2018-09-30 |
Luke Kenneth Casso... | add sv support for zeroing predication in dest register |
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2018-09-30 |
Luke Kenneth Casso... | add in predication to sv instruction execution |
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2018-09-30 |
Luke Kenneth Casso... | start linking in predication into sv |
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2018-09-30 |
Luke Kenneth Casso... | use an alternative logic for detecting scalar / loop-end |
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2018-09-30 |
Luke Kenneth Casso... | fix code template for when SPIKE_SIMPLEV is not defined |
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2018-09-29 |
Luke Kenneth Casso... | fix bug in sv template where FRS2 was checking rs3 |
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2018-09-29 |
Luke Kenneth Casso... | add checks for RVC registers to sv template |
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2018-09-29 |
Luke Kenneth Casso... | add sv_insn_t overloads for rvc registers |
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2018-09-29 |
Luke Kenneth Casso... | also arrange for id_regs.py to identify compressed... |
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2018-09-29 |
Luke Kenneth Casso... | a LOT of debugging and fixing, sv loop actually working |
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2018-09-29 |
Luke Kenneth Casso... | move SV CSRs to user-read-write |
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2018-09-29 |
Luke Kenneth Casso... | add near-duplicate of SV CFG REG CSRs, for predication |
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2018-09-29 |
Luke Kenneth Casso... | add implementation of CSR SV CFG regs 0-7 |
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2018-09-29 |
Luke Kenneth Casso... | assign SV REG CSRs (using new union ability) |
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2018-09-29 |
Luke Kenneth Casso... | make sv csr tables a union so they can be assigned... |
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2018-09-29 |
Luke Kenneth Casso... | add support for CSR_SVVL to CSRRWI as well |
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2018-09-29 |
Luke Kenneth Casso... | fix bug in CSR set SVVL: val has already been looked up |
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2018-09-29 |
Luke Kenneth Casso... | add stub for SV REG configs |
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2018-09-29 |
Luke Kenneth Casso... | stop a compiler warning |
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2018-09-29 |
Luke Kenneth Casso... | reorganise from moving sv_pred_* and sv_reg_* tables... |
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2018-09-29 |
Luke Kenneth Casso... | have to move SV CSRs into processor_t |
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2018-09-29 |
Luke Kenneth Casso... | add 8 CSRs for registers and predication each |
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2018-09-29 |
Luke Kenneth Casso... | whoops dont need separate SVSETVL/SVGETVL CSRs |
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2018-09-29 |
Luke Kenneth Casso... | revert addition of svsetvl as an actual opcode, add... |
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2018-09-29 |
Luke Kenneth Casso... | Revert "sv setvl as a csr not going to work, add getvl... |
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2018-09-29 |
Luke Kenneth Casso... | Revert "manually add svsetvl instruction" |
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2018-09-28 |
Luke Kenneth Casso... | manually add svsetvl instruction |
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2018-09-28 |
Luke Kenneth Casso... | sv setvl as a csr not going to work, add getvl only |
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2018-09-27 |
Luke Kenneth Casso... | adding sv vector length CSR to processor state, and... |
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2018-09-27 |
Luke Kenneth Casso... | add sv predication function |
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2018-09-26 |
Luke Kenneth Casso... | save some cpu cycles by |ing the checks for vectorop... |
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2018-09-26 |
Luke Kenneth Casso... | whoops vectorop has to be |= not &= to accumulate ... |
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2018-09-26 |
Luke Kenneth Casso... | cache the sv redirected register values on each loop |
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2018-09-26 |
Luke Kenneth Casso... | remembered that the use of sv registers have to be... |
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2018-09-26 |
Luke Kenneth Casso... | clarify comments on (key strategic) sv_insn_t::remap... |
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2018-09-26 |
Luke Kenneth Casso... | actually implement sv register re-mapping |
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2018-09-26 |
Luke Kenneth Casso... | ok this is tricky: an extra parameter has to be passed... |
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2018-09-26 |
Luke Kenneth Casso... | move sv remap function to sv.cc (not inline) |
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2018-09-26 |
Luke Kenneth Casso... | check if register redirection is active, and if vectori... |
tree | commitdiff |
2018-09-26 |
Luke Kenneth Casso... | comment why sv_insn_t is set up the way it is; add... |
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2018-09-26 |
Luke Kenneth Casso... | include auto-generated identification of use of registe... |
tree | commitdiff |
2018-09-26 |
Luke Kenneth Casso... | shuffle things around a bit for sv, put rv32/64_name... |
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2018-09-25 |
Luke Kenneth Casso... | add decode.h header to sv.h |
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2018-09-25 |
Luke Kenneth Casso... | rename sv vlen to sv voffs, add csr and reg tables |
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2018-09-25 |
Luke Kenneth Casso... | add reference to vector length in sv |
tree | commitdiff |
2018-09-25 |
Luke Kenneth Casso... | use sv_insn_t class in instruction template |
tree | commitdiff |
2018-09-25 |
Luke Kenneth Casso... | add sv_insn_t class (inherits from insn_t) |
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2018-09-25 |
Luke Kenneth Casso... | argh cant virtualise rd/rs1-3, due to union usage with... |
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2018-09-25 |
Luke Kenneth Casso... | sv: rd, rs1/2/3 become virtual so that sv_insn_t can... |
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2018-09-25 |
Luke Kenneth Casso... | clarify sv cam table |
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2018-09-24 |
Luke Kenneth Casso... | define CSR and register tables for SV |
tree | commitdiff |
2018-09-06 |
Tim Newsome | Merge pull request #235 from riscv/sba |
tree | commitdiff |
2018-09-05 |
Tim Newsome | Fix cut-and-paste bug in 64-bit SBA loads. |
tree | commitdiff |
2018-08-24 |
Tim Newsome | Add dummy custom debug registers, to test OpenOCD.... |
tree | commitdiff |
2018-08-24 |
Andrew Waterman | Fix several disassembler bugs |
tree | commitdiff |
2018-08-23 |
Andrew Waterman | Add --disable-dtb option to suppress writing the DTB... |
tree | commitdiff |
2018-08-22 |
Andrew Waterman | Make IRQ_COP read-only/undelegable unless coprocessor... |
tree | commitdiff |
2018-08-21 |
Andrew Waterman | Instantiate disassembler after max_xlen is known |
tree | commitdiff |
2018-08-18 |
Andrew Waterman | Don't increment instret immediately after it is written... |
tree | commitdiff |
2018-08-10 |
Tim Newsome | Fix 2 trigger corner cases. (#229) |
tree | commitdiff |
2018-07-31 |
Andrew Waterman | Make sstatus.MXR readable |
tree | commitdiff |
2018-07-23 |
SeungRyeol Lee | Fix using the uninitialized disassemble object. (#220) |
tree | commitdiff |
2018-07-10 |
Andrew Waterman | Refactor and fix LR/SC implementation (#217) |
tree | commitdiff |
2018-06-12 |
Tim Newsome | Merge pull request #212 from riscv/hartsel |
tree | commitdiff |
2018-06-11 |
Tim Newsome | Update debug_defines.h |
tree | commitdiff |
2018-05-31 |
Andy Wright | Put simif_t declaration in its own file. (#209) |
tree | commitdiff |
2018-05-18 |
Prashanth Mundkur | Fix install of missed header. (#207) |
tree | commitdiff |
2018-05-18 |
Prashanth Mundkur | Extract out device-tree generation and compilation... |
tree | commitdiff |
2018-05-04 |
Andrew Waterman | Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" |
tree | commitdiff |
2018-05-04 |
Andrew Waterman | C.LWSP and C.LDSP with rd=0 are legal instructions |
tree | commitdiff |
2018-05-01 |
Andrew Waterman | Fix commit log for serializing instructions |
tree | commitdiff |
2018-04-30 |
Andrew Waterman | Only break out of the simulator loop on WFI, not on... |
tree | commitdiff |
2018-04-05 |
Prashanth Mundkur | Allow querying the mmu configuration chosen during... |
tree | commitdiff |
2018-04-04 |
Andrew Waterman | Revert "Fix for issue #183: No illegal instruction... |
tree | commitdiff |
2018-03-30 |
Palmer Dabbelt | Merge pull request #189 from pmundkur/pm-csr-name-api |
tree | commitdiff |
2018-03-26 |
Prashanth Mundkur | Add an api to get the name for a CSR. |
tree | commitdiff |
2018-03-22 |
Andrew Waterman | Implement Hauser misa.C misalignment proposal (#187) |
tree | commitdiff |
2018-03-21 |
Prashanth Mundkur | Fix the access exception during page-table walks to... |
tree | commitdiff |
2018-03-19 |
Tim Newsome | Fix spike-dasm. (#184) |
tree | commitdiff |
2018-03-19 |
Tim Newsome | Merge pull request #182 from riscv/reset_bits |
tree | commitdiff |
2018-03-16 |
Tim Newsome | Implement debug havereset bits |
tree | commitdiff |
2018-03-16 |
Andrew Waterman | Merge branch 'deepsrc-b_fix_issue183' |
tree | commitdiff |
2018-03-16 |
Shubhodeep Roy Cho... | Fix for issue #183: No illegal instruction exception... |
tree | commitdiff |
2018-03-14 |
Prashanth Mundkur | Fix a bug caused by moving misa into state_t. (#180) |
tree | commitdiff |
2018-03-13 |
Prashanth Mundkur | Move processor.isa to state.misa, since it really belon... |
tree | commitdiff |
2018-03-10 |
Tim Newsome | Fix single stepping csrrw instructions (#178) |
tree | commitdiff |
2018-03-08 |
Tim Newsome | Merge pull request #177 from riscv/debug_auth |
tree | commitdiff |
2018-03-06 |
Prashanth Mundkur | Narrow the interface used by the processors and memory... |
tree | commitdiff |
2018-03-06 |
Prashanth Mundkur | Fix install of a missed header from debug_rom. |
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