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add a second LD request to dcache which is merged with first,
[soc.git]
/
src
/
soc
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experiment
/
test
/
test_ldst_pi_misalign.py
2022-01-08
Luke Kenneth Casso...
add a second LD request to dcache which is merged with...
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2022-01-08
Luke Kenneth Casso...
start adding in mis-aligned LD/ST support into LoadStore1
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2021-12-13
Luke Kenneth Casso...
set pr=0 because privileged mode is pr=0 not pr=1
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2021-12-13
Luke Kenneth Casso...
add in missing MSRSpec import
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2021-12-13
Tobias Platen
update MMU PortInterface Test (misalign)
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2021-12-05
Luke Kenneth Casso...
wishbone bus convert on dcache
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2021-12-04
Luke Kenneth Casso...
remove yet another duplicated copy of wb_get and add...
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2021-05-26
Luke Kenneth Casso...
add ldst PortInterface misalign unit test (underway)
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