2021-08-01 |
Jonathan Neuschäfer | soc.simple.test: Rename setup_test_memory to avoid... jn-tests |
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2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
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2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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2020-10-06 |
Luke Kenneth Casso... | skip Decode2ToOperand from PowerDecodeSubset |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-08-14 |
Luke Kenneth Casso... | fix test_compunit.py after moving decoder rdflags function |
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2020-08-14 |
Luke Kenneth Casso... | sort out instruction stop/cancel when adding a new... |
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2020-08-04 |
Luke Kenneth Casso... | msr and pc moved to "state" in PowerDecode2 |
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2020-07-31 |
Luke Kenneth Casso... | missed go_i/rel_o rename |
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2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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2020-07-26 |
Luke Kenneth Casso... | argh add yet another latch to detect when LD/ST has... |
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2020-07-26 |
Luke Kenneth Casso... | sigh, issue with detection/waiting for LD/ST CompUnit |
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2020-07-26 |
Luke Kenneth Casso... | convert LDST test to accumulator style |
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2020-07-26 |
Luke Kenneth Casso... | run subtest, indentation getting too large, move to... |
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2020-07-25 |
Luke Kenneth Casso... | wait until pipeline indicates that its output is valid... |
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2020-07-25 |
Luke Kenneth Casso... | move reset of rdmaskn to after "busy" |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-21 |
Luke Kenneth Casso... | interesting bug in test_compunit.py when there are... |
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2020-07-21 |
Luke Kenneth Casso... | move cia and msr to trap input record |
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2020-07-16 |
Luke Kenneth Casso... | get trap compunit test working, adding bigendian and msr |
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2020-07-11 |
Luke Kenneth Casso... | sorting out bigendian/littleendian including in qemu |
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2020-07-10 |
Luke Kenneth Casso... | re-add rc/oe back into LDST input record |
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2020-07-10 |
Luke Kenneth Casso... | whew panic over, missed a bigendian argument in test_co... |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-06 |
Luke Kenneth Casso... | adding mtspr tests |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-05 |
Luke Kenneth Casso... | sigh read and write xer detection, fix spr and trap... |
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2020-07-04 |
Luke Kenneth Casso... | oops initialise Function Unit class with idx |
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2020-06-28 |
Luke Kenneth Casso... | got Pi2LSUI FSM working |
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2020-06-27 |
Luke Kenneth Casso... | make Memory accessible via TestSRAMBareLoadStoreUnit |
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2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
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2020-06-22 |
Luke Kenneth Casso... | simplified L0CacheBuffer down to a "PortInterface Arbiter" |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Luke Kenneth Casso... | use while / exception in test_compunit loop |
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2020-06-17 |
Luke Kenneth Casso... | decoding assembly instruction name, move to separate... |
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2020-06-17 |
Luke Kenneth Casso... | get fu compunit test to use ISACaller instruction-memory |
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2020-06-17 |
Luke Kenneth Casso... | start to add in independent execution into ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | use an independent power decoder in ISACaller |
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2020-06-15 |
Luke Kenneth Casso... | move setup/check memory into helper functions for use... |
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2020-06-14 |
Luke Kenneth Casso... | reasonably certain that the careful and slow use of... |
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2020-06-12 |
Luke Kenneth Casso... | update ld/st test to see what is going on |
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2020-06-12 |
Luke Kenneth Casso... | tracking down what looks like an error in the Simulator... |
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2020-06-12 |
Luke Kenneth Casso... | debug printout of sim and hardware memory, shows mismat... |
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2020-06-11 |
Luke Kenneth Casso... | even more complexity in CompALUMulti, to deal with... |
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2020-06-11 |
Luke Kenneth Casso... | yield needed for unit tests to work (has to go) |
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2020-06-10 |
Luke Kenneth Casso... | whitespace |
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2020-06-10 |
Luke Kenneth Casso... | link ST.go directly to ST.rel |
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2020-06-07 |
Luke Kenneth Casso... | add missing arg to ISA in test_compunit |
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2020-06-06 |
Luke Kenneth Casso... | experimenting with setting up and testing memory |
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2020-06-06 |
Luke Kenneth Casso... | work out how to initialise memory directly |
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2020-06-06 |
Luke Kenneth Casso... | initialise L0 Memory from simulator memory |
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2020-06-06 |
Luke Kenneth Casso... | wait a little for wr.rel to activate if wrmask is active |
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2020-06-06 |
Luke Kenneth Casso... | allow Mem initialisation in ISACaller |
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2020-06-06 |
Luke Kenneth Casso... | allow Mem in Simulator to be initialised |
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2020-06-06 |
Luke Kenneth Casso... | use name of unit to write simulator/vcd file |
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2020-06-06 |
Luke Kenneth Casso... | LDSTCompUnit test data structures linked up, starting... |
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2020-06-04 |
Luke Kenneth Casso... | remove unneeded imports |
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2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
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2020-06-04 |
Luke Kenneth Casso... | connect up write-ports from Regfiles to FUs |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-03 |
Luke Kenneth Casso... | move over to using power_regspec_map.py from PowerDecod... |
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2020-06-02 |
Luke Kenneth Casso... | argh - bad hack, detecting when there are no registers... |
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2020-06-02 |
Luke Kenneth Casso... | take out unneeded code, add Settle() to see if it helps... |
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2020-06-01 |
Luke Kenneth Casso... | okaaay add a "rdflags" function which obtains the yes... |
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2020-06-01 |
Luke Kenneth Casso... | argh - need to zero the src_i input after "Read" is... |
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2020-05-31 |
Luke Kenneth Casso... | bit-test on the function-unit value being tested |
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2020-05-31 |
Luke Kenneth Casso... | add logical compunit test |
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2020-05-31 |
Luke Kenneth Casso... | remove unneeded code and inputs. convert to "naming... |
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2020-05-31 |
Luke Kenneth Casso... | split out common code from test_alu_compunit.py |
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