| 2021-05-26 |
Luke Kenneth Casso... | arse. PLL test_issuer clk_sel_i accidentally only 1... |
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| 2021-05-26 |
Luke Kenneth Casso... | remove err feature from sram4k wb |
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| 2021-05-26 |
Luke Kenneth Casso... | rename PLL signals |
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| 2021-05-24 |
Luke Kenneth Casso... | match up PLL names |
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| 2021-05-22 |
Luke Kenneth Casso... | update PLL to use Instance |
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| 2021-05-13 |
Luke Kenneth Casso... | update comments in issuer.py regarding a 4th FSM |
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| 2021-05-09 |
Luke Kenneth Casso... | add comment about LD/ST exception needs copying into... |
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| 2021-05-07 |
Luke Kenneth Casso... | whoops setup of core.sv_pred_sm/dm not indented and... |
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| 2021-05-06 |
Luke Kenneth Casso... | pass relevant predicate mask bits through to Decoders... |
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| 2021-05-06 |
Luke Kenneth Casso... | add in predicate mask bit detection when zeroing is... |
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| 2021-05-06 |
Luke Kenneth Casso... | pass SVP64 ReMap field through to core and then on... |
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| 2021-05-05 |
Luke Kenneth Casso... | whoops wrong signal name, set exc_happened |
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| 2021-05-04 |
Luke Kenneth Casso... | add TODO comments and cross-reference to bug |
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| 2021-05-04 |
Luke Kenneth Casso... | note a way to see if an exception happened, in TestIssuer |
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| 2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
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| 2021-04-25 |
Cesar Strauss | Shift-out skipped mask bits for both crpred and intpred |
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| 2021-04-24 |
Luke Kenneth Casso... | whitespace |
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| 2021-04-23 |
Luke Kenneth Casso... | more openpower-isa conversion |
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| 2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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| 2021-04-22 |
Cesar Strauss | Implement CR predication |
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| 2021-04-21 |
Cesar Strauss | CR sub-fields are stored in MSB0 order |
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| 2021-04-21 |
Cesar Strauss | Fix sense of "invert" signal |
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| 2021-04-18 |
Luke Kenneth Casso... | create signal on test_issuer which gives PLL clk_sel_i... |
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| 2021-04-18 |
Luke Kenneth Casso... | rename PLL pins to match LIP6.fr PLL |
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| 2021-04-18 |
Luke Kenneth Casso... | core_stopped_i unused: remove |
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| 2021-04-17 |
Cesar Strauss | Implement 1<<r3 directly by a shift |
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| 2021-04-10 |
Cesar Strauss | Implement 1<<r3 predicate mode |
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| 2021-04-09 |
Luke Kenneth Casso... | test firmware upload program needed to branch back... |
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| 2021-04-08 |
Luke Kenneth Casso... | sort out pc reset when DMI interface requests reset |
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| 2021-04-06 |
Cesar Strauss | Make the VL loop reentrant in HDL |
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| 2021-04-03 |
Cesar Strauss | Reminder for a possible hardware optimization |
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| 2021-04-03 |
Cesar Strauss | Be more precise when using a one-bit constant |
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| 2021-04-03 |
Cesar Strauss | Signal the simulator when completing a VL loop |
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| 2021-04-01 |
Luke Kenneth Casso... | TWI enabled in JTAG boundary scan |
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| 2021-04-01 |
Luke Kenneth Casso... | reduce subset of functions to be created in JTAG bounda... |
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| 2021-04-01 |
Luke Kenneth Casso... | bug in iverilog, segfaults due to empty case statement |
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| 2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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| 2021-03-30 |
Cesar Strauss | Skip leading zero bits on predicate masks |
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| 2021-03-28 |
Cesar Strauss | Move DECODE_SV to its place between MASK_WAIT and INSN_... |
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| 2021-03-28 |
Cesar Strauss | Move instruction decoding to after predication |
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| 2021-03-28 |
Cesar Strauss | Prepare to advance src/dst step after getting the predi... |
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| 2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
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| 2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
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| 2021-03-24 |
Luke Kenneth Casso... | comment about using PriorityEncoder |
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| 2021-03-22 |
Luke Kenneth Casso... | do not set sv_changed |
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| 2021-03-22 |
Luke Kenneth Casso... | make sure non-svp64-mode works |
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| 2021-03-22 |
Luke Kenneth Casso... | have get_predint return indicator that mask is all 1s |
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| 2021-03-22 |
Cesar Strauss | Skip fetching integer predicate mask when register... |
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| 2021-03-22 |
Cesar Strauss | Decode and fetch integer predicate registers |
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| 2021-03-21 |
Cesar Strauss | Fix typo |
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| 2021-03-21 |
Cesar Strauss | Add unique name to decoded predication signals |
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| 2021-03-21 |
Cesar Strauss | Revert removal of *.value from Enums |
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| 2021-03-21 |
Cesar Strauss | Fix syntax |
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| 2021-03-21 |
Luke Kenneth Casso... | more TODO comments |
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| 2021-03-21 |
Luke Kenneth Casso... | add for-loop pseudocode for CR predicate mask reading |
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| 2021-03-21 |
Luke Kenneth Casso... | code comments in TestIssuer |
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| 2021-03-21 |
Cesar Strauss | Start work on the predicate fetch FSM |
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| 2021-03-20 |
Luke Kenneth Casso... | more pseudocode in TestIssuer |
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| 2021-03-20 |
Luke Kenneth Casso... | add harmless code and commented-out pseudocode for... |
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| 2021-03-19 |
Luke Kenneth Casso... | more comments for TestIssuer when adding predication |
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| 2021-03-19 |
Luke Kenneth Casso... | comments for TestIssuer get_predint and get_predcr |
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| 2021-03-19 |
Luke Kenneth Casso... | add more pieces of predication reading puzzle to TestIssuer |
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| 2021-03-19 |
Luke Kenneth Casso... | cleanup TestIssuer (comments) |
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| 2021-03-19 |
Luke Kenneth Casso... | spelling |
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| 2021-03-19 |
Luke Kenneth Casso... | code-shuffle in TestIssuer, split out setting up periph... |
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| 2021-03-19 |
Luke Kenneth Casso... | move duplicated code to a function in TestIssuer |
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| 2021-03-18 |
Luke Kenneth Casso... | more hint/comments |
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| 2021-03-18 |
Luke Kenneth Casso... | update TestIssuer comments |
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| 2021-03-18 |
Luke Kenneth Casso... | add comments on most likely place to put predicate... |
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| 2021-03-18 |
Luke Kenneth Casso... | comments TestIssuer, add a stub FSM |
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| 2021-03-17 |
Luke Kenneth Casso... | add SVP64 dststep incrementing in PowerDecoder2, Testis... |
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| 2021-03-14 |
Cesar Strauss | Activate the VL==0 loop with any SVP64 prefix whatsoever |
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| 2021-03-12 |
Luke Kenneth Casso... | use PowerDecoder2.loop_continue instead of no_out_vec |
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| 2021-03-11 |
Luke Kenneth Casso... | add link of RA_OR_ZERO SVP64 detection |
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| 2021-03-09 |
Cesar Strauss | Create a new signal for the Simulator to wait on |
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| 2021-03-08 |
Luke Kenneth Casso... | actually make it possible to disable svp64 on commandli... |
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| 2021-03-08 |
Cesar Strauss | Remove the unused internal insn_done signal |
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| 2021-03-08 |
Cesar Strauss | Fix argument order to match function declaration |
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| 2021-03-07 |
Cesar Strauss | Merge WAIT_RESET into INSN_FETCH on the Issue FSM |
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| 2021-03-07 |
Luke Kenneth Casso... | move DMI stuff to separate function in issuer.py |
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| 2021-03-07 |
Luke Kenneth Casso... | update comments in issuer.py |
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| 2021-03-07 |
Cesar Strauss | Implement the VL==0 loop |
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| 2021-03-06 |
Cesar Strauss | Allow updating the PC and SVSTATE registers while stopped |
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| 2021-03-06 |
Cesar Strauss | Begin to implement the Simple-V loop |
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| 2021-03-06 |
Cesar Strauss | Do not reset pc_changed and sv_changed at instruction end |
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| 2021-03-06 |
Cesar Strauss | Make the raw opcode input port of the decoder stay... |
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| 2021-03-05 |
Luke Kenneth Casso... | litex expects wishbone "err" signals even if not used |
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| 2021-03-05 |
Cesar Strauss | Move writing of the PC state register to the issue FSM |
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| 2021-03-05 |
Cesar Strauss | Move the wait on "core stop" out of fetch, and into... |
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| 2021-03-03 |
Luke Kenneth Casso... | cur_state is a global, does not have to be passed as... |
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| 2021-03-03 |
Luke Kenneth Casso... | add svstate_i to TestIssuer which mirrors pc_i |
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| 2021-02-26 |
Luke Kenneth Casso... | remove sv_changed input to fetch_fsm, add it to issue_f... |
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| 2021-02-26 |
Luke Kenneth Casso... | moving new_svstate and update_svstate into issue FSM... |
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| 2021-02-26 |
Luke Kenneth Casso... | move fetch_insn_o into issue_fsm TestIssuer |
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| 2021-02-26 |
Luke Kenneth Casso... | add comments, missing that VL loop ends after execution... |
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| 2021-02-26 |
Cesar Strauss | Implement a decode/issue FSM between fetch and execute |
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| 2021-02-23 |
Luke Kenneth Casso... | add note that SVSTATE has changed, this will allow... |
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| 2021-02-22 |
Luke Kenneth Casso... | move setting of NIA into fetch FSM in TestIssuer |
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| 2021-02-22 |
Luke Kenneth Casso... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
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| 2021-02-22 |
Luke Kenneth Casso... | rename inter-FSM handshake signals in TestIssuer |
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