soc.git
3 years agomight have RADIXMMU at least semi-working... maybe
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 15:13:18 +0000 (16:13 +0100)]
might have RADIXMMU at least semi-working... maybe

3 years agouse assertEqual in RADIXMMU unit test
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 14:04:23 +0000 (15:04 +0100)]
use assertEqual in RADIXMMU unit test

3 years agoskip 1-pred check if m= used in SVP64Asm
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 13:20:27 +0000 (14:20 +0100)]
skip 1-pred check if m= used in SVP64Asm

3 years agoEnable VCOMPRESS test case
Cesar Strauss [Tue, 30 Mar 2021 12:47:56 +0000 (09:47 -0300)]
Enable VCOMPRESS test case

VEXPAND seems to have some issue in the Simulator maybe.

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 12:35:14 +0000 (13:35 +0100)]
submodule update

3 years agoAdd new twin predication case
Cesar Strauss [Tue, 30 Mar 2021 12:27:11 +0000 (09:27 -0300)]
Add new twin predication case

Equivalent to VCOMPRESS followed by VEXPAND.

3 years agoAdjust twin predication cases for the new syntax
Cesar Strauss [Tue, 30 Mar 2021 12:22:25 +0000 (09:22 -0300)]
Adjust twin predication cases for the new syntax

3 years agoSkip leading zero bits on predicate masks
Cesar Strauss [Tue, 30 Mar 2021 11:57:48 +0000 (08:57 -0300)]
Skip leading zero bits on predicate masks

The PRED_SKIP state moves src/dst step to the next non-zero bit on the
mask.
The leading zeros on the mask (plus the set bit) are shifted out, while
the shifted amount is added to the step.
If the new step value would increase past VL, the loop is ended.

3 years agouse port name for INT regfile to match up with test_runner gtkw
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 11:34:40 +0000 (12:34 +0100)]
use port name for INT regfile to match up with test_runner gtkw

3 years agocorrections to Makefile for building / not-building 4k sram ls180
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 11:29:56 +0000 (12:29 +0100)]
corrections to Makefile for building / not-building 4k sram ls180

3 years agoMemory port seems to have been renamed
Cesar Strauss [Tue, 30 Mar 2021 11:21:09 +0000 (08:21 -0300)]
Memory port seems to have been renamed

3 years agobit of munging of Makefile, new targets
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:38:44 +0000 (11:38 +0100)]
bit of munging of Makefile, new targets

3 years agowhoops Makefile error
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:22:17 +0000 (11:22 +0100)]
whoops Makefile error

3 years agocorrect segment check (off by one in LE/BE convert
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 19:05:11 +0000 (20:05 +0100)]
correct segment check (off by one in LE/BE convert

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:18:44 +0000 (19:18 +0100)]
update submodule

3 years agosort out pywriter.py when run with no args
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:18:33 +0000 (19:18 +0100)]
sort out pywriter.py when run with no args

3 years agoremove "install" from run_sim dependency in Makefile
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:31:11 +0000 (18:31 +0100)]
remove "install" from run_sim dependency in Makefile

3 years agosvp64-enable passed through to PowerDecoderSubsets in core.py
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 22:57:45 +0000 (23:57 +0100)]
svp64-enable passed through to PowerDecoderSubsets in core.py

3 years agowhoops spelling mistake in SPRreduced Enums
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 22:56:36 +0000 (23:56 +0100)]
whoops spelling mistake in SPRreduced Enums

3 years agoMove DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE
Cesar Strauss [Sun, 28 Mar 2021 18:18:28 +0000 (15:18 -0300)]
Move DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE

3 years agoMove instruction decoding to after predication
Cesar Strauss [Sun, 28 Mar 2021 18:03:24 +0000 (15:03 -0300)]
Move instruction decoding to after predication

Since predication can update SRCSTEP and DESTSTEP, leave decoding for
after their final values are known.
So, "DECODE_SV" is now responsible for decoding, and sits in line between
"MASK_WAIT" and "INSN_EXECUTE".

3 years agoPrepare to advance src/dst step after getting the predicate mask
Cesar Strauss [Sun, 28 Mar 2021 16:57:36 +0000 (13:57 -0300)]
Prepare to advance src/dst step after getting the predicate mask

3 years agorather invasive reduction of SPR regfile size
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 15:48:53 +0000 (16:48 +0100)]
rather invasive reduction of SPR regfile size
done by dynamically creating an alternative SPR Enum

3 years agoadd option to reduce number of regfile ports (get DFFs down in ls180)
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:53:20 +0000 (14:53 +0100)]
add option to reduce number of regfile ports (get DFFs down in ls180)

3 years agoreduce number of regfile ports
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:37:16 +0000 (14:37 +0100)]
reduce number of regfile ports

3 years agoreduce regfile port usage on non-svp64
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:29:37 +0000 (14:29 +0100)]
reduce regfile port usage on non-svp64

3 years agoradixmmu.py: cleanup, documentation
Tobias Platen [Thu, 25 Mar 2021 19:33:22 +0000 (20:33 +0100)]
radixmmu.py: cleanup, documentation

3 years agofix _get_prtable_addr, cleanup
Tobias Platen [Thu, 25 Mar 2021 19:24:49 +0000 (20:24 +0100)]
fix _get_prtable_addr, cleanup

3 years agocomment about using PriorityEncoder
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 18:59:42 +0000 (18:59 +0000)]
comment about using PriorityEncoder

3 years agodebug output
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 17:11:00 +0000 (17:11 +0000)]
debug output

3 years agoadd comment skipping in pagereader.py
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 17:06:29 +0000 (17:06 +0000)]
add comment skipping in pagereader.py

3 years agomake svp64 isa caller unit tests more obvious
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 16:10:00 +0000 (16:10 +0000)]
make svp64 isa caller unit tests more obvious

3 years agoadd option to stop writing isa all.py in pseudocode directory
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 15:44:39 +0000 (15:44 +0000)]
add option to stop writing isa all.py in pseudocode directory

3 years agofix nonzero test in ISACaller RADIXMMU
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 09:27:29 +0000 (09:27 +0000)]
fix nonzero test in ISACaller RADIXMMU

3 years agoadd --disable-svp64 to litex sim build
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 09:26:36 +0000 (09:26 +0000)]
add --disable-svp64 to litex sim build

3 years agomake addrshift human readable
Tobias Platen [Tue, 23 Mar 2021 20:51:03 +0000 (21:51 +0100)]
make addrshift human readable

3 years agoadd addrshift function (based on microwatt)
Tobias Platen [Tue, 23 Mar 2021 20:09:58 +0000 (21:09 +0100)]
add addrshift function (based on microwatt)

3 years agodo not set sv_changed
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 23:51:06 +0000 (23:51 +0000)]
do not set sv_changed

3 years agotestcase for _get_pgtable_addr
Tobias Platen [Mon, 22 Mar 2021 20:21:28 +0000 (21:21 +0100)]
testcase for _get_pgtable_addr

3 years agoread predicate mask from correct point in SVP64Asm
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:33:14 +0000 (17:33 +0000)]
read predicate mask from correct point in SVP64Asm

3 years agoadd SVP64Asm option for "m=" to set both src and dest mask
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:30:58 +0000 (17:30 +0000)]
add SVP64Asm option for "m=" to set both src and dest mask

3 years agoadd very small dff sram variant (no 4k SRAMs)
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:14:25 +0000 (17:14 +0000)]
add very small dff sram variant (no 4k SRAMs)

3 years agoAdd test cases for integer VCOMPRESS and VEXPAND
Cesar Strauss [Mon, 22 Mar 2021 11:46:22 +0000 (08:46 -0300)]
Add test cases for integer VCOMPRESS and VEXPAND

In these cases, either srcmask or destmask is "always", so the
corresponding mask should be all ones, instead of being fetched from the
register file.

3 years agomake sure non-svp64-mode works
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:40:35 +0000 (12:40 +0000)]
make sure non-svp64-mode works

3 years agohave get_predint return indicator that mask is all 1s
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:12:06 +0000 (12:12 +0000)]
have get_predint return indicator that mask is all 1s

3 years agoSkip fetching integer predicate mask when register number is zero
Cesar Strauss [Mon, 22 Mar 2021 10:34:09 +0000 (07:34 -0300)]
Skip fetching integer predicate mask when register number is zero

3 years agoAdd traces for the new FSM and integer predicate decoding
Cesar Strauss [Mon, 22 Mar 2021 00:52:47 +0000 (21:52 -0300)]
Add traces for the new FSM and integer predicate decoding

3 years agoDecode and fetch integer predicate registers
Cesar Strauss [Mon, 22 Mar 2021 00:26:11 +0000 (21:26 -0300)]
Decode and fetch integer predicate registers

3 years agoFix typo
Cesar Strauss [Sun, 21 Mar 2021 21:41:06 +0000 (18:41 -0300)]
Fix typo

3 years agoAdd unique name to decoded predication signals
Cesar Strauss [Sun, 21 Mar 2021 21:14:54 +0000 (18:14 -0300)]
Add unique name to decoded predication signals

3 years agoRevert removal of *.value from Enums
Cesar Strauss [Sun, 21 Mar 2021 20:53:21 +0000 (17:53 -0300)]
Revert removal of *.value from Enums

3 years agoFix syntax
Cesar Strauss [Sun, 21 Mar 2021 18:03:28 +0000 (15:03 -0300)]
Fix syntax

3 years agomore TODO comments
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 18:03:29 +0000 (18:03 +0000)]
more TODO comments

3 years agoadd for-loop pseudocode for CR predicate mask reading
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 14:48:01 +0000 (14:48 +0000)]
add for-loop pseudocode for CR predicate mask reading

3 years agocode comments in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:25:26 +0000 (13:25 +0000)]
code comments in TestIssuer

3 years agoadjust syntax of SVP64 predicate test cas
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:18:30 +0000 (13:18 +0000)]
adjust syntax of SVP64 predicate test cas

3 years agonaah. back to "sv." syntax for SVP64 assembly
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:17:26 +0000 (13:17 +0000)]
naah.  back to "sv." syntax for SVP64 assembly

3 years agoStart work on the predicate fetch FSM
Cesar Strauss [Sun, 21 Mar 2021 13:02:19 +0000 (10:02 -0300)]
Start work on the predicate fetch FSM

After an instruction arrives, it will decode the SVP64 mask part
and will fetch the masks from the register files.
At the moment, it just returns the all ones mask.
The Issue FSM calls it, after receiving an instruction from Fetch, and
before entering execution vector loop.

3 years agoAdd predication test case, initially disabled
Cesar Strauss [Sun, 21 Mar 2021 11:44:09 +0000 (08:44 -0300)]
Add predication test case, initially disabled

Directly derived from a test in test_caller_svp64_predication.py
The goal is to incrementally develop the TestIssuer FSMs, until it passes.

3 years agoadd override for build commands powerpc64-linux-gnu-{ENVVAR}
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 11:07:59 +0000 (11:07 +0000)]
add override for build commands powerpc64-linux-gnu-{ENVVAR}

3 years agoenable -mregnames in assembly syntax for unit tests
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 10:55:01 +0000 (10:55 +0000)]
enable -mregnames in assembly syntax for unit tests

3 years agomore pseudocode in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:58:54 +0000 (18:58 +0000)]
more pseudocode in TestIssuer

3 years agomove radixmmu to unit test format
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:51:41 +0000 (18:51 +0000)]
move radixmmu to unit test format

3 years agoadd harmless code and commented-out pseudocode for predication in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:29:01 +0000 (18:29 +0000)]
add harmless code and commented-out pseudocode for predication in TestIssuer

3 years agosort out predicate zeroing in ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 11:22:23 +0000 (11:22 +0000)]
sort out predicate zeroing in ISACaller

3 years agoattempting to add src/dest-zeroing to ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 00:12:06 +0000 (00:12 +0000)]
attempting to add src/dest-zeroing to ISACaller

3 years agomore comments for TestIssuer when adding predication
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 23:40:38 +0000 (23:40 +0000)]
more comments for TestIssuer when adding predication

3 years agotestcase for _get_pgtable_addr
Tobias Platen [Fri, 19 Mar 2021 19:33:22 +0000 (20:33 +0100)]
testcase for _get_pgtable_addr

3 years agodecode predicate src/dest zeroing in SVP64RMModeDecode
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 19:12:11 +0000 (19:12 +0000)]
decode predicate src/dest zeroing in SVP64RMModeDecode

3 years agocomments for TestIssuer get_predint and get_predcr
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:45:01 +0000 (14:45 +0000)]
comments for TestIssuer get_predint and get_predcr

3 years agoadd more pieces of predication reading puzzle to TestIssuer
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:37:17 +0000 (14:37 +0000)]
add more pieces of predication reading puzzle to TestIssuer

3 years agocleanup TestIssuer (comments)
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:17:00 +0000 (14:17 +0000)]
cleanup TestIssuer (comments)

3 years agospelling
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:14:10 +0000 (14:14 +0000)]
spelling

3 years agocode-shuffle in TestIssuer, split out setting up peripherals
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:12:44 +0000 (14:12 +0000)]
code-shuffle in TestIssuer, split out setting up peripherals

3 years agomove duplicated code to a function in TestIssuer
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:04:23 +0000 (14:04 +0000)]
move duplicated code to a function in TestIssuer

3 years agomore hint/comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:26:04 +0000 (21:26 +0000)]
more hint/comments

3 years agocomments / code-shuffle
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:23:53 +0000 (21:23 +0000)]
comments / code-shuffle

3 years agoupdate TestIssuer comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:16:21 +0000 (21:16 +0000)]
update TestIssuer comments

3 years agoadd comments on most likely place to put predicate mask read-firing
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 20:02:32 +0000 (20:02 +0000)]
add comments on most likely place to put predicate mask read-firing

3 years agocomments TestIssuer, add a stub FSM
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 19:15:38 +0000 (19:15 +0000)]
comments TestIssuer, add a stub FSM

3 years agoadd MSR PR read in RADIXMMU ISACaller
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:45:38 +0000 (18:45 +0000)]
add MSR PR read in RADIXMMU ISACaller

3 years agore-add auto-generated file simplev.py to gitignore
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:34:07 +0000 (18:34 +0000)]
re-add auto-generated file simplev.py to gitignore
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=d3767842a2f8f66f9e3de882a36592bfa3d344b8;hp=3f8a17ca49a1cc9636b85b41b84a0a88476cbdf8

3 years agore-add nmigen-type-annotations with libre-soc url
Jacob Lifshay [Thu, 18 Mar 2021 16:42:45 +0000 (09:42 -0700)]
re-add nmigen-type-annotations with libre-soc url

3 years agoexperiment in radixmmu with returning addr_next (and some error messages)
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 14:42:40 +0000 (14:42 +0000)]
experiment in radixmmu with returning addr_next (and some error messages)

3 years agoadd sv_out2 to PowerDecode and PowerDecoder2
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:24:54 +0000 (12:24 +0000)]
add sv_out2 to PowerDecode and PowerDecoder2
used for 2nd write (currently LD/ST update only)

3 years agocross-reference to bug #619
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:15:00 +0000 (12:15 +0000)]
cross-reference to bug #619

3 years agoadd auto-generation of out2 column in SVP64RM
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:13:20 +0000 (12:13 +0000)]
add auto-generation of out2 column in SVP64RM
needed for PowerDecoder2 as well as microwatt svp64 vhdl generation

3 years agoremove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:48:14 +0000 (11:48 +0000)]
remove nmigen-type-annotations temporarily

3 years agoremove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:47:07 +0000 (11:47 +0000)]
remove nmigen-type-annotations temporarily

3 years agoadd option to move RS in CSV file reading, for compatibility with microwatt
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:22:05 +0000 (11:22 +0000)]
add option to move RS in CSV file reading, for compatibility with microwatt
decode1.vhdl;

3 years agocorrect comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:33:15 +0000 (22:33 +0000)]
correct comments

3 years agore-enable SVP64 ISACaller predicate tests
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:29:07 +0000 (22:29 +0000)]
re-enable SVP64 ISACaller predicate tests

3 years agoadd ascii graphic for extsw svp64 operation
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:25:21 +0000 (22:25 +0000)]
add ascii graphic for extsw svp64 operation

3 years agoadd more explanatory comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:21:12 +0000 (22:21 +0000)]
add more explanatory comments

3 years agoadd twin-predicated extsw SVP64 ISACaller unit test
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:15:58 +0000 (22:15 +0000)]
add twin-predicated extsw SVP64 ISACaller unit test

3 years agoadd SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 21:29:49 +0000 (21:29 +0000)]
add SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller

3 years agoadd CR-based predication to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 20:40:49 +0000 (20:40 +0000)]
add CR-based predication to ISACaller

3 years agocleanup raduxmmu._walk_tree
Tobias Platen [Wed, 17 Mar 2021 19:13:40 +0000 (20:13 +0100)]
cleanup raduxmmu._walk_tree

3 years agocreate iterative mmu lookup loop
Tobias Platen [Wed, 17 Mar 2021 18:59:12 +0000 (19:59 +0100)]
create iterative mmu lookup loop

3 years agoadd SVP64 INT-style predication to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 15:20:02 +0000 (15:20 +0000)]
add SVP64 INT-style predication to ISACaller