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[WIP] Add initial version of Aquila LPC slave core
2022-03-01 Raptor Engineering... [WIP] Add initial version of Aquila LPC slave core
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2022-03-01 Raptor Engineering... Add missing mapping between HAS and USE for Liteeth...
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2022-02-23 Raptor Engineering... Formally release this version of Tercel under the GNU...
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2022-02-23 Raptor Engineering... Fix typo
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2022-02-23 Raptor Engineering... Make Tercel register map a bit easier to read
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2022-02-23 Raptor Engineering... Update Tercel README with actual core state on reset
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2022-02-23 Raptor Engineering... Add Tercel support to Arty
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2022-02-23 Raptor Engineering... Add initial Tercel support for Arctic Tern
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2022-02-22 Raptor Engineering... Add initial Arctic Tern support
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2022-02-22 Raptor Engineering... Extend LiteDRAM VHDL wrapper to allow more than one...
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2022-02-22 Joel Stanleyyosys: Use read_verilog
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