| 2021-12-22 |
Luke Kenneth Casson... | when setting DSISR in LoadStore1 use correct load bit...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | use correct X-Form L field in OP_MTMSRD
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | check problem state in OP_MTMSRD from original reg...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops, use MSR.IR for I-Cache fetch!
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove unneeded state in LoadStore1
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on exception WAIT_MMU ACK in...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear out instr_fault when exception is thrown
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on idle/valid in Loadstore1
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | ooo far too late at night to be doing this
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove bus_ack (found bug in Simulation, sorted)
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | bug in mmu setting radix tree size with one extra bit
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | continue to assert PC in FetchFSM if needed
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | enable I-Cache wishbone memory type in issuer_verilog...
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | whoops issuer_verilog.py enabling mmu has to pass microwatt_mmu
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | for each unit test case in test_issuer_mmu_data_path...
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | test_issuer_mmu_data_path.py needs to use wb_get because of
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu code-comments
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | comments
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | use prtbl in proc_tbl_wait in mmu
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu.py comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | set up DAR correctly in unit tests, added set_ldst_spr...
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | unit tests for SPRs when MMU enabled,
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | code-comments in MMU
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | prefer not to invert when doing if/else.
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add RTPDE - Radit Tree Page Directory Entry - Record...
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add (and ues) PRTBL Record in MMU
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | create PGTBL Record and use it in MMU page_table_idle
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add hard stop address in ifetch unit test, bit of a...
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | set terminate if core terminate requested
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add DMI STOPADDR register and use it in HDLRunner to...
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | break out when core is stopped in HDLRunner
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add link to XICS bugreport
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | sort out reset signalling after tracking down Simulation...
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add icache/dcache/mmu unit test for TestIssuer
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | get instructions to re-run in issuer after I-Cache...
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | forgot to connect up I-Cache to MMU
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | move connection of bus.stall in icache.py,
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tidyup
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tlb_req_index is TLB_BITS long not TLB_SIZE
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops, a Simulation bug, dcache bus ack Signal needed...
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | give names to MMU records
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | set_mmu_spr was using the slow-SPR index for the regfile
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops remove duplicate code (cut/paste error) no harm...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more unneeded code
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | read MSR.PR and MSR.DR and update ICache priv/virt...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more of SVP64 from TestIssuerInternalInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove update of pc, msr and svstate from TestIssuerInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move update of pc, msr and svstate into TestIssuerBase
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | comment-out TestIssuerInternalInorder for now
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move alternative TestIssuerInternalInOrder to new file
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | split out common elaboratable code from TestIssuer,
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | big split-out of common functions in TestIssuer to...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | simplifying / tidyup of TestIssuer to get CoreState
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | sort out MSR, read/write in same way as PC/SVSTATE...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | whoops accidentally commented out setup of instructions
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | get fetch_failed working with no MMU
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | trying to get TestIssuer FSM to respond correctly to...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | get OP_FETCH_FAILED to respond/return an exception...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | update wb_get memory with instructions if required
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | MMU LOOKUP for fetch failed, priv mode is inversion...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | link MSR.PR into MMU FSM OP_FETCH_FAILED
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | return temporarily to older version of pinmux submodule
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | request a flush of icache to clear the instruction...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix test_loadstore1.py with MSR=PR/DR
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | set pr=0 because privileged mode is pr=0 not pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add in missing MSRSpec import
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | commented-out code
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix up pr/dr/sf in PortInterfaceBase
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | pass in new MSRSpec to test_loadstore1.py not msr_pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert PortInterfaceBase to pass msr not msr_pr
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert LoadStore1 to new msr.pr/dr/sf
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add msr to MMU Op Subset record
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | still have to import MSRSpec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | connect up PortInterface priv_mode, virt_mode and mode_32bit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | construct an MSRSpec in PortInterfaceBase (not used...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | whoops wrong variable names
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | rename msr_pr to priv_mode in LDSTCompUnit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | TODO comments about using MSRspec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | change PortInterface naming to msr not msr_pr in set_wr_addr
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set and reset instruction fault so it does not occur...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | when an exception happens, if it is a fetch_failed...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | delay MMU LOOKUP done by one clock so that the exception...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring MMU exception out where AllFunctionUnits (and...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring exception out from MMU FSM, correct "done"
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | add LDSTException output to MMU
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | drat, a test inverting the instruction made it into...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | starting to hack in fetch failed (including OP_FETCH_FAILED)
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | print debugs established that when a wb_get memory...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set fetch_failed into PowerDecoder2 combinatorially
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | in a terrible botched way, get at I-Cache and set it up
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | fix bug in unit test, forgot that wb_get mem dict is...
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | get FetchUnitInterface I-Cache test working (sort-of)
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | comment out broken test
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | whoops forgot to add pspec
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | add start of test_loadstore1_ifetch_unit_interface()
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commit | commitdiff | tree |
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