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document branch pipeline relationship with PowerDecode2
2020-07-15
Luke Kenneth Casson...
document branch pipeline relationship with PowerDecode2
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2020-07-15
Luke Kenneth Casson...
simplify instr_is_priv
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2020-07-15
Luke Kenneth Casson...
move traptype to soc.consts
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2020-07-15
Luke Kenneth Casson...
add better comments on mul overflow
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2020-07-15
Luke Kenneth Casson...
test privileged rfid call
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2020-07-15
Luke Kenneth Casson...
spelling error
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2020-07-15
Luke Kenneth Casson...
range of testing overflow was incorrect in mul
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2020-07-15
Luke Kenneth Casson...
set MSR up properly for privileged mtmsr test
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2020-07-15
Luke Kenneth Casson...
whoops forgot to update PC after trap in ISACaller
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2020-07-15
Luke Kenneth Casson...
move priv test to above illegal/trap test
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2020-07-15
Luke Kenneth Casson...
comments on IntegerData class
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2020-07-15
Luke Kenneth Casson...
import PipeContext not FPPipeContext
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2020-07-15
Luke Kenneth Casson...
minor reorg on PowerDecoder2, use switch/case rather...
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2020-07-15
Luke Kenneth Casson...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
use case statement in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
select RA based on LDSTMode.update in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
add cache cx to LDSTMode
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2020-07-15
Luke Kenneth Casson...
remove unused class XerBits
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2020-07-15
Luke Kenneth Casson...
use Record Assert and also check muxid
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2020-07-15
Luke Kenneth Casson...
no need to check individual port members, just check...
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2020-07-14
Luke Kenneth Casson...
cookie-cut setup from alu proof_main_stage.py
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2020-07-14
Luke Kenneth Casson...
reduce code size by using CompOpSubsetBase for ALU...
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2020-07-14
Luke Kenneth Casson...
split out CompOpSubsetBase (meaning to do for a while)
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2020-07-14
Luke Kenneth Casson...
update docstrings
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2020-07-14
Luke Kenneth Casson...
adding MSR.PR unit test intended to activate privileged...
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2020-07-14
Luke Kenneth Casson...
attempting to access self.msr directly
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2020-07-14
Luke Kenneth Casson...
set up masks for OP_RL* formal proof
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2020-07-14
Luke Kenneth Casson...
add priv instruction checking to ISACaller simulator
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2020-07-14
Luke Kenneth Casson...
add in privileged instruction decision-making in PowerDecode2
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2020-07-14
Luke Kenneth Casson...
add MSR reading to issue FSM
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2020-07-14
Luke Kenneth Casson...
comments on PowerDecode2
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2020-07-14
Luke Kenneth Casson...
add MSR to PowerDecoder2
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2020-07-14
Luke Kenneth Casson...
disable cxxsim test
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2020-07-14
Luke Kenneth Casson...
attempting running cxxsim on ALU pipeline test
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2020-07-14
Luke Kenneth Casson...
first attempt running cxxsim
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2020-07-13
Luke Kenneth Casson...
whitespace
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2020-07-13
Luke Kenneth Casson...
formal proof of OP_EXTSWSLI
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2020-07-13
Luke Kenneth Casson...
quick test showing how left/right mask work
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2020-07-13
Luke Kenneth Casson...
add mtmsrd instruction and unit test
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2020-07-13
Luke Kenneth Casson...
comments
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2020-07-13
Luke Kenneth Casson...
attempting formal proof of OP_EXTSWSLI
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2020-07-13
Luke Kenneth Casson...
reduce rotl module to one line (use bit_select)
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2020-07-13
Luke Kenneth Casson...
document rb as sh
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2020-07-13
Luke Kenneth Casson...
increase range of test values for extswsli
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2020-07-13
Luke Kenneth Casson...
add EXTSWSLI "pass" to formal shift_rot proof
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2020-07-13
Luke Kenneth Casson...
remove unneeded spec patching
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2020-07-13
Luke Kenneth Casson...
enable extswsli tests, fix spec-patching
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2020-07-13
Luke Kenneth Casson...
add regression test, simulator is wrong
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2020-07-13
Luke Kenneth Casson...
add simulator test against qemu for extswsli
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2020-07-13
Luke Kenneth Casson...
fix read of sliced register
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2020-07-13
Luke Kenneth Casson...
not perfect but close enough: add read registers RA...
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2020-07-13
Luke Kenneth Casson...
add extswsli unit test
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2020-07-13
Luke Kenneth Casson...
add link to rotator, sign-extend mode OP_EXTSWSLI
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2020-07-12
Luke Kenneth Casson...
rename InternalOp to MicrOp
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2020-07-12
Luke Kenneth Casson...
attempting to get test_trap_sim working, seems to switch...
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2020-07-12
Luke Kenneth Casson...
submodule update
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2020-07-12
Luke Kenneth Casson...
add OP_ATTN test back in
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2020-07-12
Luke Kenneth Casson...
exit FSM when termination detected
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2020-07-12
Luke Kenneth Casson...
code-morph on core connect_instruction
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2020-07-12
Luke Kenneth Casson...
modify PowerDecoder to read LDSTMode correctly
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2020-07-12
Luke Kenneth Casson...
change CSV LD/ST update field to LDSTMode (support...
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2020-07-12
Luke Kenneth Casson...
return unsigned int from binary reading
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2020-07-12
Luke Kenneth Casson...
update submodule
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2020-07-12
Luke Kenneth Casson...
missed setting of link register on OP_BC in PowerDecoder2
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2020-07-12
Luke Kenneth Casson...
msb of instruction causing sign-overflow
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2020-07-12
Luke Kenneth Casson...
add std and stdu ldst unit tests
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2020-07-12
Luke Kenneth Casson...
update-mode request write signalled too early
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2020-07-11
Luke Kenneth Casson...
sort out core write latching: gate by busy, and use...
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2020-07-11
Luke Kenneth Casson...
* clarifying core function unit enable
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2020-07-11
Luke Kenneth Casson...
add bigendian flag
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2020-07-11
Luke Kenneth Casson...
add endian
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2020-07-11
Luke Kenneth Casson...
fix spr setting, set endianness
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2020-07-11
Luke Kenneth Casson...
sigh spelling
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2020-07-11
Luke Kenneth Casson...
add bigendian
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2020-07-11
Luke Kenneth Casson...
more setting bigendian
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2020-07-11
Luke Kenneth Casson...
add bigendian mode to helloworld test
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2020-07-11
Luke Kenneth Casson...
sort out big/little endian startup on qemu
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2020-07-11
Luke Kenneth Casson...
sorting out bigendian/littleendian including in qemu
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2020-07-11
Luke Kenneth Casson...
whoops output trunc_divs not trunc_div
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2020-07-11
Luke Kenneth Casson...
add random mulhd and mulld tests
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2020-07-11
Luke Kenneth Casson...
enable mul tests after sorting pseudo-code mul overflow
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2020-07-11
Luke Kenneth Casson...
special test for mul hw to cope with ignoring OE flag
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2020-07-10
Luke Kenneth Casson...
add a DIVS function as separate and discrete from floor_div
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2020-07-10
Luke Kenneth Casson...
add random unsigned div tests
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2020-07-10
Luke Kenneth Casson...
add overflow div tests
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2020-07-10
Luke Kenneth Casson...
propagate missing parameters from div
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2020-07-10
Luke Kenneth Casson...
code comments
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2020-07-10
Luke Kenneth Casson...
do not set div result if overflow occurs
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2020-07-10
Luke Kenneth Casson...
re-enable div random tests and other regressions
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2020-07-10
Luke Kenneth Casson...
check for div_overflow equal to None rather than == 1
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2020-07-10
Luke Kenneth Casson...
re-add rc/oe back into LDST input record
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2020-07-10
Luke Kenneth Casson...
whew panic over, missed a bigendian argument in test_compunit.py
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2020-07-10
Luke Kenneth Casson...
add test7 div regression
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2020-07-10
Luke Kenneth Casson...
add more debug output for #425
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2020-07-10
Luke Kenneth Casson...
add debugging chain for #425
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2020-07-10
Luke Kenneth Casson...
update submodule
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2020-07-10
Luke Kenneth Casson...
cut/paste error writing to wrong vcd file
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2020-07-09
Luke Kenneth Casson...
add regression test for div overflow case
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2020-07-09
Luke Kenneth Casson...
slightly different so handling in common output stage
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