soc.git
2021-04-15 Luke Kenneth... add icachemmu option to ISACaller
2021-04-14 Luke Kenneth... submodule update
2021-04-14 Luke Kenneth... whitespace
2021-04-14 Luke Kenneth... submodule update
2021-04-14 Tobias Platenupdate test_caller_radix.py
2021-04-14 Tobias Platenradixmmu: handle badtree
2021-04-14 Tobias Platenupdate test case for radix mmu
2021-04-14 Tobias Platenradixmmu: error handling
2021-04-13 Tobias Platenmore fixes for radixmmu.py
2021-04-13 Tobias Platenfix AttributeError in radixmmu testcase
2021-04-12 Tobias Platenradixmmu.py: cleanup
2021-04-11 Tobias Platenfix bug in radixmmu.py
2021-04-11 Tobias Platenradixmmu: more work on segment check
2021-04-10 Cesar StraussImplement 1<<r3 predicate mode
2021-04-10 Cesar StraussAdd 1<<r3 test cases to TestIssuer
2021-04-10 Cesar StraussAdd test cases for 1<<r3 predication
2021-04-09 Luke Kenneth... add blinken lights assembly (not used yet)
2021-04-09 Luke Kenneth... test firmware upload program needed to branch back...
2021-04-08 Luke Kenneth... sort out pc reset when DMI interface requests reset
2021-04-08 Luke Kenneth... submodule update
2021-04-08 Luke Kenneth... argh, wb jtag stall probably is not working
2021-04-08 Luke Kenneth... upload over 32-bit JTAG Wishbone
2021-04-08 Luke Kenneth... shrink JTAG master bus to 32-bit (match with litex)
2021-04-07 Luke Kenneth... submodule update
2021-04-07 Tobias PlatenWIP: calculate address of first page table entry
2021-04-07 Tobias Platenradixmmu: fix segment_check function and its caller
2021-04-06 Luke Kenneth... 4k SRAM Instance needs write-enable @ 8-bit width
2021-04-06 Luke Kenneth... 8-bit granularity on JTAG wishbone
2021-04-06 Luke Kenneth... remove unneeded code
2021-04-06 Staf Verhaegensoc-cocotb-sim submodule update
2021-04-06 Tobias Platenadd mmu_states.dia
2021-04-06 Luke Kenneth... git submodule update
2021-04-06 Cesar StraussMake the VL loop reentrant in HDL
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of...
2021-04-06 Cesar StraussStart the test case from a point where the predicate...
2021-04-05 Luke Kenneth... litex submodule update
2021-04-05 Luke Kenneth... submodule update
2021-04-04 Staf Verhaegensoc-cocotb-sim submodule update
2021-04-04 Cesar StraussAdd test case for reentrant VL loop
2021-04-03 Cesar StraussReminder for a possible hardware optimization
2021-04-03 Cesar StraussBe more precise when using a one-bit constant
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero
2021-04-03 Cesar StraussAdd a test case for integer single predication
2021-04-03 Cesar StraussDisallow unknown encmodes in SVP64 Assembly
2021-04-03 Cesar StraussEnable remaining disabled test cases
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-04-03 Cesar StraussSignal the simulator when completing a VL loop
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd twin predication test
2021-04-02 Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussAdd VEXPAND test case for the ISA Simulator
2021-04-02 Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
2021-04-02 Cesar StraussPut sanity check inside the existing '2Pred' case,...
2021-04-02 Cesar StraussEnforce explicit src/dest masks on CR twin-predication
2021-04-02 Cesar StraussDisallow mixing of sm=xx and/or dm=xx with m=xx on...
2021-04-02 Cesar StraussDisallow dm=xx on single predication
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussReally enforce sm=xx not being allowed on single-pred
2021-04-02 Cesar StraussKeep mask mode flags separate
2021-04-01 Luke Kenneth... git submodule update
2021-04-01 Luke Kenneth... TWI enabled in JTAG boundary scan
2021-04-01 Luke Kenneth... git submodule update
2021-04-01 Luke Kenneth... reduce subset of functions to be created in JTAG bounda...
2021-04-01 Luke Kenneth... use OrderedDict to restore exact order from JSON file
2021-04-01 Luke Kenneth... add soc-cocotb-sim submodule
2021-04-01 Luke Kenneth... submodule update
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-04-01 Luke Kenneth... bug in iverilog, segfaults due to empty case statement
2021-04-01 Luke Kenneth... add no pll ls180 build
2021-04-01 Staf Verhaegenlibresoc-litex submodule update
2021-03-31 Tobias Platen_new_lookup: remove unused argument mbits
2021-03-31 Tobias Platenradixmmu: read prtable entry
2021-03-31 Tobias Platenradixmmu.py: remove redunant code
2021-03-31 Luke Kenneth... submodule update
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platenmore work on _prtable_lookup and testcase
2021-03-30 Luke Kenneth... add comments
2021-03-30 Luke Kenneth... use PRTBL SPR in RADIXMMU
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platencomment about microwatt implementation details
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Luke Kenneth... add comments, correct load addresses
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Alain D D WilliamsAllow comments
2021-03-30 Tobias Platenadd function _prtable_lookup and unit test
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Luke Kenneth... might have RADIXMMU at least semi-working... maybe
2021-03-30 Luke Kenneth... use assertEqual in RADIXMMU unit test
2021-03-30 Luke Kenneth... skip 1-pred check if m= used in SVP64Asm
2021-03-30 Cesar StraussEnable VCOMPRESS test case
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Cesar StraussAdd new twin predication case
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax
2021-03-30 Cesar StraussSkip leading zero bits on predicate masks
2021-03-30 Luke Kenneth... use port name for INT regfile to match up with test_run...
2021-03-30 Luke Kenneth... corrections to Makefile for building / not-building...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-30 Luke Kenneth... bit of munging of Makefile, new targets
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