soc.git
2021-12-25 Luke Kenneth... add mmu.bin test2 to much simpler test_loadstore1.py
2021-12-25 Luke Kenneth... move msr in test_loadstore1.py outside of conditional...
2021-12-25 Luke Kenneth... whitespace
2021-12-25 Luke Kenneth... move microwatt mmu.bin test 3 page table to test pageta...
2021-12-25 Luke Kenneth... wait for MMU "done" when setting PRTBL and PIDR
2021-12-25 Luke Kenneth... add microwatt mmu.bin regression test test_mmu_3
2021-12-24 Luke Kenneth... enable instruction redirect in mmu ifetch test
2021-12-23 Luke Kenneth... somehow managed to miss out setting r1.forward_valid1...
2021-12-23 Luke Kenneth... uniquify names in dcache.py
2021-12-23 Luke Kenneth... allow MSR reset to default to a value set by issuer_ver...
2021-12-23 Luke Kenneth... pass in msr_reset to issuer_verilog.py
2021-12-23 Luke Kenneth... add ability to set the reset values of RegFileArray
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute.
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped.
2021-12-22 Luke Kenneth... only use a single variable for ack adjusting in dcache.py
2021-12-22 Luke Kenneth... fix issues with running core in DMI "stopped" status...
2021-12-22 Luke Kenneth... when setting DSISR in LoadStore1 use correct load bit...
2021-12-22 Luke Kenneth... use correct X-Form L field in OP_MTMSRD
2021-12-22 Luke Kenneth... check problem state in OP_MTMSRD from original reg...
2021-12-22 Luke Kenneth... whoops, use MSR.IR for I-Cache fetch!
2021-12-22 Luke Kenneth... remove unneeded state in LoadStore1
2021-12-22 Luke Kenneth... clear instruction fault on exception WAIT_MMU ACK in...
2021-12-22 Luke Kenneth... clear out instr_fault when exception is thrown
2021-12-22 Luke Kenneth... clear instruction fault on idle/valid in Loadstore1
2021-12-22 Luke Kenneth... ooo far too late at night to be doing this
2021-12-22 Luke Kenneth... whoops use C not Const
2021-12-22 Luke Kenneth... whoops use C not Const
2021-12-22 Luke Kenneth... remove bus_ack (found bug in Simulation, sorted)
2021-12-22 Luke Kenneth... bug in mmu setting radix tree size with one extra bit
2021-12-21 Luke Kenneth... continue to assert PC in FetchFSM if needed
2021-12-21 Luke Kenneth... enable I-Cache wishbone memory type in issuer_verilog...
2021-12-21 Luke Kenneth... whoops issuer_verilog.py enabling mmu has to pass micro...
2021-12-21 Luke Kenneth... for each unit test case in test_issuer_mmu_data_path...
2021-12-21 Luke Kenneth... test_issuer_mmu_data_path.py needs to use wb_get because of
2021-12-21 Luke Kenneth... mmu code-comments
2021-12-21 Luke Kenneth... comments
2021-12-21 Luke Kenneth... use prtbl in proc_tbl_wait in mmu
2021-12-21 Luke Kenneth... mmu.py comments
2021-12-20 Luke Kenneth... set up DAR correctly in unit tests, added set_ldst_spr...
2021-12-20 Luke Kenneth... unit tests for SPRs when MMU enabled,
2021-12-20 Luke Kenneth... more code-comments
2021-12-20 Luke Kenneth... code-comments in MMU
2021-12-20 Luke Kenneth... prefer not to invert when doing if/else.
2021-12-20 Luke Kenneth... more code-comments
2021-12-20 Luke Kenneth... add RTPDE - Radit Tree Page Directory Entry - Record...
2021-12-20 Luke Kenneth... add (and ues) PRTBL Record in MMU
2021-12-20 Luke Kenneth... create PGTBL Record and use it in MMU page_table_idle
2021-12-19 Luke Kenneth... add hard stop address in ifetch unit test, bit of a...
2021-12-19 Luke Kenneth... set terminate if core terminate requested
2021-12-19 Luke Kenneth... code-comments
2021-12-19 Luke Kenneth... add DMI STOPADDR register and use it in HDLRunner to...
2021-12-19 Luke Kenneth... break out when core is stopped in HDLRunner
2021-12-18 Luke Kenneth... add link to XICS bugreport
2021-12-18 Luke Kenneth... sort out reset signalling after tracking down Simulatio...
2021-12-18 Luke Kenneth... add icache/dcache/mmu unit test for TestIssuer
2021-12-18 Luke Kenneth... get instructions to re-run in issuer after I-Cache...
2021-12-18 Luke Kenneth... forgot to connect up I-Cache to MMU
2021-12-18 Luke Kenneth... move connection of bus.stall in icache.py,
2021-12-18 Luke Kenneth... tidyup
2021-12-18 Luke Kenneth... tlb_req_index is TLB_BITS long not TLB_SIZE
2021-12-16 Luke Kenneth... whoops, a Simulation bug, dcache bus ack Signal needed...
2021-12-16 Luke Kenneth... give names to MMU records
2021-12-16 Luke Kenneth... set_mmu_spr was using the slow-SPR index for the regfile
2021-12-16 Luke Kenneth... whoops remove duplicate code (cut/paste error) no harm...
2021-12-15 Luke Kenneth... remove more unneeded code
2021-12-15 Luke Kenneth... read MSR.PR and MSR.DR and update ICache priv/virt...
2021-12-15 Luke Kenneth... remove more of SVP64 from TestIssuerInternalInOrder
2021-12-15 Luke Kenneth... remove update of pc, msr and svstate from TestIssuerInOrder
2021-12-15 Luke Kenneth... move update of pc, msr and svstate into TestIssuerBase
2021-12-15 Luke Kenneth... comment-out TestIssuerInternalInorder for now
2021-12-15 Luke Kenneth... move alternative TestIssuerInternalInOrder to new file
2021-12-15 Luke Kenneth... split out common elaboratable code from TestIssuer,
2021-12-15 Luke Kenneth... big split-out of common functions in TestIssuer to...
2021-12-15 Luke Kenneth... simplifying / tidyup of TestIssuer to get CoreState
2021-12-15 Luke Kenneth... sort out MSR, read/write in same way as PC/SVSTATE...
2021-12-15 Luke Kenneth... whoops accidentally commented out setup of instructions
2021-12-15 Luke Kenneth... get fetch_failed working with no MMU
2021-12-14 Tobias Platentest_loadstore1.py: test_loadstore1_ifetch_multi now...
2021-12-14 Luke Kenneth... trying to get TestIssuer FSM to respond correctly to...
2021-12-14 Luke Kenneth... get OP_FETCH_FAILED to respond/return an exception...
2021-12-14 Luke Kenneth... update wb_get memory with instructions if required
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi() in test_loadstore1.py
2021-12-14 Tobias Platenwip test case for virtual address fetch using fetch...
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi()
2021-12-14 Jonathan NeuschäferGitLab-CI: Increase clone depth
2021-12-14 Luke Kenneth... MMU LOOKUP for fetch failed, priv mode is inversion...
2021-12-14 Luke Kenneth... link MSR.PR into MMU FSM OP_FETCH_FAILED
2021-12-13 Luke Kenneth... return temporarily to older version of pinmux submodule
2021-12-13 Luke Kenneth... request a flush of icache to clear the instruction...
2021-12-13 Tobias Platentry to get multi test running
2021-12-13 Tobias Platencomments about test_loadstore1_ifetch()
2021-12-13 Luke Kenneth... fix test_loadstore1.py with MSR=PR/DR
2021-12-13 Luke Kenneth... set pr=0 because privileged mode is pr=0 not pr=1
2021-12-13 Luke Kenneth... add in missing MSRSpec import
2021-12-13 Luke Kenneth... commented-out code
2021-12-13 Tobias Platenupdate MMU PortInterface Test (misalign)
2021-12-13 Tobias Platencleanup test_ldst_pi.py
2021-12-13 Tobias Platenupdate old TestMicrowattMemoryPortInterface
2021-12-13 Tobias Platenreplace msr_pr with msr
2021-12-13 Tobias Platencleanup test_dcbz_pi.py
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