src/ieee754/fpmul/mul0.py

   1 # IEEE Floating Point Muler (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Elaboratable
   6 from nmigen.cli import main, verilog
   7
   8 from ieee754.fpcommon.fpbase import FPNumBaseRecord
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.denorm import FPSCData
  11 from ieee754.fpcommon.getop import FPBaseData
  12
  13
  14 class FPMulStage0Data:
  15
  16     def __init__(self, width, id_wid, op_wid=None):
  17         FPBaseData.__init__(self, 0, width, id_wid, op_wid)
  18         self.z = FPNumBaseRecord(width, False)
  19         self.out_do_z = Signal(reset_less=True)
  20         self.oz = Signal(width, reset_less=True)
  21         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  22         self.product = Signal(mw, reset_less=True)
  23
  24     def eq(self, i):
  25         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  26                 self.product.eq(i.product)] + FPBaseData.eq(self, i)
  27
  28
  29 class FPMulStage0Mod(Elaboratable):
  30
  31     def __init__(self, width, id_wid, op_wid=None):
  32         self.width = width
  33         self.id_wid = id_wid
  34         self.op_wid = op_wid
  35         self.i = self.ispec()
  36         self.o = self.ospec()
  37
  38     def ispec(self):
  39         return FPSCData(self.width, self.id_wid, False, self.op_wid)
  40
  41     def ospec(self):
  42         return FPMulStage0Data(self.width, self.id_wid, self.op_wid)
  43
  44     def process(self, i):
  45         return self.o
  46
  47     def setup(self, m, i):
  48         """ links module to inputs and outputs
  49         """
  50         m.submodules.mul0 = self
  51         m.d.comb += self.i.eq(i)
  52
  53     def elaborate(self, platform):
  54         m = Module()
  55         #m.submodules.mul0_in_a = self.i.a
  56         #m.submodules.mul0_in_b = self.i.b
  57         #m.submodules.mul0_out_z = self.o.z
  58
  59         # store intermediate tests (and zero-extended mantissas)
  60         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  61         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  62         m.d.comb += [
  63                      am0.eq(Cat(self.i.a.m, 0)),
  64                      bm0.eq(Cat(self.i.b.m, 0))
  65                     ]
  66         # same-sign (both negative or both positive) mul mantissas
  67         with m.If(~self.i.out_do_z):
  68             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  69                          self.o.product.eq(am0 * bm0 * 4),
  70                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  71                 ]
  72
  73         m.d.comb += self.o.oz.eq(self.i.oz)
  74         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  75         m.d.comb += self.o.mid.eq(self.i.mid)
  76         if self.o.op_wid:
  77             m.d.comb += self.o.op.eq(self.i.op)
  78         return m
  79
  80
  81 class FPMulStage0(FPState):
  82     """ First stage of mul.
  83     """
  84
  85     def __init__(self, width, id_wid):
  86         FPState.__init__(self, "multiply_0")
  87         self.mod = FPMulStage0Mod(width)
  88         self.o = self.mod.ospec()
  89
  90     def setup(self, m, i):
  91         """ links module to inputs and outputs
  92         """
  93         self.mod.setup(m, i)
  94
  95         # NOTE: these could be done as combinatorial (merge mul0+mul1)
  96         m.d.sync += self.o.eq(self.mod.o)
  97
  98     def action(self, m):
  99         m.next = "multiply_1"