src/ieee754/fpmul/mul0.py

   1 # IEEE Floating Point Muler (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Elaboratable
   6 from nmigen.cli import main, verilog
   7
   8 from ieee754.fpcommon.fpbase import FPNumBase
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.denorm import FPSCData
  11
  12
  13 class FPMulStage0Data:
  14
  15     def __init__(self, width, id_wid):
  16         self.z = FPNumBase(width, False)
  17         self.out_do_z = Signal(reset_less=True)
  18         self.oz = Signal(width, reset_less=True)
  19         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  20         self.product = Signal(mw, reset_less=True)
  21         self.mid = Signal(id_wid, reset_less=True)
  22
  23     def eq(self, i):
  24         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  25                 self.product.eq(i.product), self.mid.eq(i.mid)]
  26
  27
  28 class FPMulStage0Mod(Elaboratable):
  29
  30     def __init__(self, width, id_wid):
  31         self.width = width
  32         self.id_wid = id_wid
  33         self.i = self.ispec()
  34         self.o = self.ospec()
  35
  36     def ispec(self):
  37         return FPSCData(self.width, self.id_wid)
  38
  39     def ospec(self):
  40         return FPMulStage0Data(self.width, self.id_wid)
  41
  42     def process(self, i):
  43         return self.o
  44
  45     def setup(self, m, i):
  46         """ links module to inputs and outputs
  47         """
  48         m.submodules.mul0 = self
  49         m.d.comb += self.i.eq(i)
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53         m.submodules.mul0_in_a = self.i.a
  54         m.submodules.mul0_in_b = self.i.b
  55         m.submodules.mul0_out_z = self.o.z
  56
  57         # store intermediate tests (and zero-extended mantissas)
  58         seq = Signal(reset_less=True)
  59         mge = Signal(reset_less=True)
  60         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  61         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  62         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
  63                      mge.eq(self.i.a.m >= self.i.b.m),
  64                      am0.eq(Cat(self.i.a.m, 0)),
  65                      bm0.eq(Cat(self.i.b.m, 0))
  66                     ]
  67         # same-sign (both negative or both positive) mul mantissas
  68         with m.If(~self.i.out_do_z):
  69             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  70                          self.o.product.eq(am0 * bm0 * 4),
  71                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  72                 ]
  73
  74         m.d.comb += self.o.oz.eq(self.i.oz)
  75         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  76         m.d.comb += self.o.mid.eq(self.i.mid)
  77         return m
  78
  79
  80 class FPMulStage0(FPState):
  81     """ First stage of mul.
  82     """
  83
  84     def __init__(self, width, id_wid):
  85         FPState.__init__(self, "multiply_0")
  86         self.mod = FPMulStage0Mod(width)
  87         self.o = self.mod.ospec()
  88
  89     def setup(self, m, i):
  90         """ links module to inputs and outputs
  91         """
  92         self.mod.setup(m, i)
  93
  94         # NOTE: these could be done as combinatorial (merge mul0+mul1)
  95         m.d.sync += self.o.eq(self.mod.o)
  96
  97     def action(self, m):
  98         m.next = "multiply_1"