add links, add bitmanip logic ops

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 41191640cb3398d51b0e9fc8185da9445eedd887..a08f9967b44bb942d21376063f00db92bdf15032 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -81,6 +81,9 @@ Progress:
 * <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
+* <https://news.ycombinator.com/item?id=21112341>
+* <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
+* <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
 
 # Information Resources and Tutorials
 

diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index 6b78aa19876e13927127f64a5f3b094bc43c16be..bc52fb7633cf9a2cdf55f6c941992a9be344d7f0 100644 (file)
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -22,6 +22,38 @@ adequate.  Some exceptions however present themselves from RVV.
 
 ## logical bit-wise instructions
 
+These are the available bitwise instructions in RVV:
+
+    vmand.mm vd, vs2, vs1     # vd[i] =   vs2[i].LSB &&  vs1[i].LSB
+    vmnand.mm vd, vs2, vs1    # vd[i] = !(vs2[i].LSB &&  vs1[i].LSB)
+    vmandnot.mm vd, vs2, vs1  # vd[i] =   vs2[i].LSB && !vs1[i].LSB
+    vmxor.mm  vd, vs2, vs1    # vd[i] =   vs2[i].LSB ^^  vs1[i].LSB
+    vmor.mm  vd, vs2, vs1     # vd[i] =   vs2[i].LSB ||  vs1[i].LSB
+    vmnor.mm  vd, vs2, vs1    # vd[i] = !(vs2[i[.LSB ||  vs1[i].LSB)
+    vmornot.mm  vd, vs2, vs1  # vd[i] =   vs2[i].LSB || !vs1[i].LSB
+    vmxnor.mm vd, vs2, vs1    # vd[i] = !(vs2[i].LSB ^^  vs1[i].LSB)
+
+The ones that exist in scalar RISC-V are:
+
+    AND rd, rs1, rs2          # rd = rs1 & rs2
+    OR  rd, rs1, rs2          # rd = rs1 | rs2
+    XOR rd, rs1, rs2          # rd = rs1 ^ rs2
+
+The ones in Bitmanip are:
+
+    ANDN rd, rs1, rs2         # rd = rs1 & ~rs2
+    ORN  rd, rs1, rs2         # rd = rs1 | ~rs2
+    XORN rd, rs1, rs2         # rd = rs1 ^ ~rs2
+
+This leaves:
+
+    NOR
+    NAND
+
+These are currently listed as "pseudo-ops" in BitManip-Draft (0.91)
+They need to be actual opcodes.
+
+
 TODO: there is an extensive table in RVV of bit-level operations:
 
 output  instruction     pseudoinstruction