2024-04-14 |
Cesar Strauss | ls2: add support for the Nexys Video board master |
tree | commitdiff |
2024-04-13 |
Cesar Strauss | ls2: avoid using DRIVE attribute on Xilinx devices... |
tree | commitdiff |
2024-04-13 |
Cesar Strauss | ls2: fix keyword for declaring pin voltage type on... |
tree | commitdiff |
2022-09-13 |
Tobias Platen | undo deletion of line defining toolchain for orangecrab |
tree | commitdiff |
2022-09-12 |
Tobias Platen | add core_clk_freq variable |
tree | commitdiff |
2022-08-07 |
Tobias Platen | comment out reset signal for iverilog simulation |
tree | commitdiff |
2022-08-03 |
Tobias Platen | more work on orangecrab dram |
tree | commitdiff |
2022-07-20 |
Tobias Platen | merge part 2 of Cesar's patch |
tree | commitdiff |
2022-07-15 |
Tobias Platen | optionally add ECLKBRIDGECS to ECP5CRG |
tree | commitdiff |
2022-07-06 |
Tobias Platen | fixed KeyError for rcs_arctic_tern_bmc_card |
tree | commitdiff |
2022-06-30 |
Tobias Platen | set dram_clk_freq to None |
tree | commitdiff |
2022-05-17 |
Tobias Platen | orangecrab: don't use async. set to 50 mhz. |
tree | commitdiff |
2022-05-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2022-05-15 |
Tobias Platen | set dram_clk_freq = 100.0e6 for orangecrab |
tree | commitdiff |
2022-05-04 |
Luke Kenneth Casso... | pass in freq setting to nextpnr-xilinx |
tree | commitdiff |
2022-05-04 |
Luke Kenneth Casso... | add micron n25q 128mb QSPI device to table of |
tree | commitdiff |
2022-05-04 |
Luke Kenneth Casso... | add tercel speed-up but missing id for arty a7 at the... |
tree | commitdiff |
2022-05-03 |
Tobias Platen | begin dram support for ls2 |
tree | commitdiff |
2022-05-02 |
Tobias Platen | add spi for orangecrab |
tree | commitdiff |
2022-04-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2022-04-30 |
Tobias Platen | change frequency for orangecrab, correct uart output |
tree | commitdiff |
2022-04-30 |
Luke Kenneth Casso... | nope, 24 mhz works, 27 does not |
tree | commitdiff |
2022-04-30 |
Luke Kenneth Casso... | update arty a7 clock frequency to 27 mhz, works with... |
tree | commitdiff |
2022-04-24 |
Luke Kenneth Casso... | doh |
tree | commitdiff |
2022-04-24 |
Luke Kenneth Casso... | list of hyperrams not just one |
tree | commitdiff |
2022-04-22 |
Luke Kenneth Casso... | move hyperram to 0x0000_00000 and 0x2000_0000 |
tree | commitdiff |
2022-04-22 |
Luke Kenneth Casso... | add second hyperram module, for arty-a7, |
tree | commitdiff |
2022-04-16 |
Luke Kenneth Casso... | put versa_ecp5 back to synchronous at 50 mhz to test... |
tree | commitdiff |
2022-04-16 |
Luke Kenneth Casso... | remove stall from WBASyncBridges on master side |
tree | commitdiff |
2022-04-16 |
Luke Kenneth Casso... | attempting to get VERSA_ECP5 and Icarus Sim to work... |
tree | commitdiff |
2022-04-16 |
Luke Kenneth Casso... | add in extra delay-for-core in ECP5CRG |
tree | commitdiff |
2022-04-16 |
Tobias Platen | orangecrab: set clock frequency, remove ignored iostandard |
tree | commitdiff |
2022-04-15 |
Luke Kenneth Casso... | comment about UARTResource for orangecrab |
tree | commitdiff |
2022-04-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2022-04-15 |
Tobias Platen | add orangecrab uart and toolchain |
tree | commitdiff |
2022-04-15 |
Luke Kenneth Casso... | checking simulation of Async DDR3 |
tree | commitdiff |
2022-04-15 |
Luke Kenneth Casso... | work-in-progress |
tree | commitdiff |
2022-04-15 |
Luke Kenneth Casso... | reorg of the ECP5 Clock-Reset to be able to add |
tree | commitdiff |
2022-04-15 |
Tobias Platen | whitespace |
tree | commitdiff |
2022-04-15 |
Tobias Platen | add orangecrab to list of supported boards |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | reduce versa_ecp5 clock freq to 50 mhz, reduce bit... |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | add default args in DDR3SoC |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | put fw_addr back to 0xff00_0000, xics.bin test passed |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | move firmware to address 0x0 to test microwatt xics.bin |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | bleh. add XICS_ICS and XICS_ICP but the patch is |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | code-comments for when ASyncBridge is deployed |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | add new dram_clk_freq argument which does nothing for now |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | add an extra domain dramsync2x in preparation for |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | add a dramsync2x domain as well |
tree | commitdiff |
2022-04-14 |
Luke Kenneth Casso... | move 2x-clock-and-dividing into separate function in... |
tree | commitdiff |
2022-04-13 |
Luke Kenneth Casso... | get microwatt-verilator sim running at different boot... |
tree | commitdiff |
2022-04-12 |
Luke Kenneth Casso... | add comments on locations where async bridge needs... |
tree | commitdiff |
2022-04-11 |
Luke Kenneth Casso... | too big, shift down to 2MB offset |
tree | commitdiff |
2022-04-11 |
Luke Kenneth Casso... | fix coldboot to boot from return address |
tree | commitdiff |
2022-04-11 |
Luke Kenneth Casso... | put versa_ecp5 below 50 mhz as a bodge-way to stop... |
tree | commitdiff |
2022-04-10 |
Luke Kenneth Casso... | Revert "Wire up missing CRG / DDR3 clock control /... |
tree | commitdiff |
2022-04-10 |
Luke Kenneth Casso... | Revert "Put sysclk2x back under system reset control" |
tree | commitdiff |
2022-04-10 |
Raptor Engineering... | Put sysclk2x back under system reset control |
tree | commitdiff |
2022-04-09 |
Luke Kenneth Casso... | add QSPI dump back in (smaller one) to check it is... |
tree | commitdiff |
2022-04-09 |
Raptor Engineering... | Wire up missing CRG / DDR3 clock control / reset signals |
tree | commitdiff |
2022-04-09 |
Luke Kenneth Casso... | shuffle addresses around a bit |
tree | commitdiff |
2022-04-08 |
Luke Kenneth Casso... | add DRAM offset into SYSCON and jump to DRAM if flash... |
tree | commitdiff |
2022-04-08 |
Luke Kenneth Casso... | add ELF reading to coldboot.c, move spi address to... |
tree | commitdiff |
2022-04-08 |
Luke Kenneth Casso... | add read of SYSCON and entry for SPIFlash |
tree | commitdiff |
2022-04-08 |
Luke Kenneth Casso... | up the delay-time on ddr3 reset, put loop around dram... |
tree | commitdiff |
2022-04-08 |
Luke Kenneth Casso... | comment/80-char limit |
tree | commitdiff |
2022-04-07 |
Raptor Engineering... | Enable DDR3 using a 50MHz clock on Versa 85 |
tree | commitdiff |
2022-04-07 |
Raptor Engineering... | Move simulation HyperRAM pins off of DDR3 pins |
tree | commitdiff |
2022-04-06 |
Luke Kenneth Casso... | add QSPI support to arty_a7 |
tree | commitdiff |
2022-04-04 |
Luke Kenneth Casso... | allow setting individual directions on QSPI dq0-dq3 |
tree | commitdiff |
2022-04-04 |
Luke Kenneth Casso... | sigh put firmware.hex qspi file in correct place |
tree | commitdiff |
2022-04-04 |
Luke Kenneth Casso... | increase power-on-delay for icarus sim to allow reset... |
tree | commitdiff |
2022-04-04 |
Luke Kenneth Casso... | disable ethmac for now, pass firmware.hex to cypress... |
tree | commitdiff |
2022-04-04 |
Luke Kenneth Casso... | redo start address of firmware so it can be specified... |
tree | commitdiff |
2022-04-04 |
Raptor Engineering... | Fix SPI device simulation model MISO/MOSI wiring |
tree | commitdiff |
2022-04-02 |
Raptor Engineering... | Add 10/100 MAC pins for Versa boards and enable MAC |
tree | commitdiff |
2022-03-31 |
Luke Kenneth Casso... | got icarus verilog model of QSPI working and it returns... |
tree | commitdiff |
2022-03-31 |
Luke Kenneth Casso... | whitespace cleanup |
tree | commitdiff |
2022-03-31 |
Raptor Engineering... | Fix Tercel QSPI master connections |
tree | commitdiff |
2022-03-31 |
Luke Kenneth Casso... | remove {err} feature from Tercel |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | add err wishbone feature to Tercel |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | remove clk from spi_flash, |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | add qspi module to arty_a7 |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | use nmigen_boards naming conventions for SPIFlash |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | update comments, link/setup of peripherals |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | add TODO comments about using platform.add_resources |
tree | commitdiff |
2022-03-29 |
Luke Kenneth Casso... | whitespace cleanup, 80 char limit |
tree | commitdiff |
2022-03-29 |
Raptor Engineering... | Add initial integration for OpenCores 10/100 Ethernet MAC |
tree | commitdiff |
2022-03-28 |
Raptor Engineering... | Fix instructions in comment |
tree | commitdiff |
2022-03-27 |
Luke Kenneth Casso... | set reset from ResetSignal not straight to 1 for HyperRAM |
tree | commitdiff |
2022-03-27 |
Luke Kenneth Casso... | try latency of 7 for winbond hyperram |
tree | commitdiff |
2022-03-27 |
Luke Kenneth Casso... | set upper CSns on HyperRAM to zero and set reset_n HI |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | add clock output on hyperram sim |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | add all 4 CSn lines for Quad HyperRAM PMOD |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | grr |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | reduce power-on-delay bits to 2 for icarus sim ecp5 |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | remove switches from hyperram iverilog test |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | remove unneeded model variable |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | add missing ECP5 model OBZ.v and rename testbench |
tree | commitdiff |
2022-03-26 |
Luke Kenneth Casso... | sort out platform IO pads for iverilog hyperram sim |
tree | commitdiff |
next |