src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23 import math
  24
  25 # project module imports
  26 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  27 from parse import Parse
  28 from bsv.actual_pinmux import init
  29 from bsv.bus_transactors import axi4_lite
  30
  31 copyright = '''
  32 /*
  33    This BSV file has been generated by the PinMux tool available at:
  34    https://bitbucket.org/casl/pinmux.
  35
  36    Authors: Neel Gala, Luke
  37    Date of generation: ''' + time.strftime("%c") + '''
  38 */
  39 '''
  40 header = copyright + '''
  41 package pinmux;
  42
  43    typedef struct{
  44       Bit#(1) outputval;      // output from core to pad                bit7
  45       Bit#(1) output_en;      // output enable from core to pad         bit6
  46       Bit#(1) input_en;       // input enable from core to io_cell      bit5
  47       Bit#(1) pullup_en;      // pullup enable from core to io_cell     bit4
  48       Bit#(1) pulldown_en;    // pulldown enable from core to io_cell   bit3
  49       Bit#(1) drivestrength;  // drivestrength from core to io_cell     bit2
  50       Bit#(1) pushpull_en;    // pushpull enable from core to io_cell   bit1
  51       Bit#(1) opendrain_en;   // opendrain enable form core to io_cell  bit0
  52    } GenericIOType deriving(Eq,Bits,FShow);
  53
  54 '''
  55 footer = '''
  56      endinterface;
  57    endmodule
  58 endpackage
  59 '''
  60
  61
  62 def pinmuxgen(pth=None, verify=True):
  63     """ populating the file with the code
  64     """
  65
  66     p = Parse(pth, verify)
  67     ifaces = Interfaces(pth)
  68     ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  69     init(p, ifaces)
  70
  71     bp = 'bsv_src'
  72     if pth:
  73         bp = os.path.join(pth, bp)
  74     if not os.path.exists(bp):
  75         os.makedirs(bp)
  76     bl = os.path.join(bp, 'bsv_lib')
  77     if not os.path.exists(bl):
  78         os.makedirs(bl)
  79
  80     cwd = os.path.split(__file__)[0]
  81
  82     # copy over template and library files
  83     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  84                 os.path.join(bp, 'Makefile'))
  85     cwd = os.path.join(cwd, 'bsv_lib')
  86     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
  87         shutil.copyfile(os.path.join(cwd, fname),
  88                     os.path.join(bl, fname))
  89
  90     bus = os.path.join(bp, 'busenable.bsv')
  91     pmp = os.path.join(bp, 'pinmux.bsv')
  92     ptp = os.path.join(bp, 'PinTop.bsv')
  93     bvp = os.path.join(bp, 'bus.bsv')
  94
  95     write_pmp(pmp, p, ifaces)
  96     write_ptp(ptp, p, ifaces)
  97     write_bvp(bvp, p, ifaces)
  98     write_bus(bus, p, ifaces)
  99
 100
 101 def write_bus(bus, p, ifaces):
 102     # package and interface declaration followed by
 103     # the generic io_cell definition
 104     with open(bus, "w") as bsv_file:
 105         ifaces.busfmt(bsv_file)
 106
 107
 108 def get_cell_bit_width(p):
 109     max_num_cells = 0
 110     for cell in p.muxed_cells:
 111             max_num_cells = max(len(cell)-1, max_num_cells)
 112     return int(math.log(max_num_cells, 2))
 113
 114 def write_pmp(pmp, p, ifaces):
 115     # package and interface declaration followed by
 116     # the generic io_cell definition
 117     with open(pmp, "w") as bsv_file:
 118         bsv_file.write(header)
 119
 120         bsv_file.write('''\
 121    interface MuxSelectionLines;
 122
 123       // declare the method which will capture the user pin-mux
 124       // selection values.The width of the input is dependent on the number
 125       // of muxes happening per IO. For now we have a generalized width
 126       // where each IO will have the same number of muxes.''')
 127
 128         for cell in p.muxed_cells:
 129             cnum = 'Bit#(' + str(int(math.log(len(cell) - 1, 2))) + ')'
 130             bsv_file.write(mux_interface.ifacefmt(cell[0], cnum))
 131
 132         bsv_file.write('''
 133       endinterface
 134
 135       interface PeripheralSide;
 136       // declare the interface to the IO cells.
 137       // Each IO cell will have 8 input field (output from pin mux
 138       // and on output field (input to pinmux)''')
 139         # ==============================================================
 140
 141         # == create method definitions for all peripheral interfaces ==#
 142         ifaces.ifacefmt(bsv_file)
 143
 144         # ==============================================================
 145
 146         # ===== finish interface definition and start module definition=======
 147         bsv_file.write('''
 148    endinterface
 149
 150    interface Ifc_pinmux;
 151       interface MuxSelectionLines mux_lines;
 152       interface PeripheralSide peripheral_side;
 153    endinterface
 154    (*synthesize*)
 155    module mkpinmux(Ifc_pinmux);
 156 ''')
 157         # ====================================================================
 158
 159         # ======================= create wire and registers =================#
 160         bsv_file.write('''
 161       // the followins wires capture the pin-mux selection
 162       // values for each mux assigned to a CELL
 163 ''')
 164         cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
 165         for cell in p.muxed_cells:
 166             bsv_file.write(mux_interface.wirefmt(
 167                 cell[0], cell_bit_width))
 168
 169         ifaces.wirefmt(bsv_file)
 170
 171         bsv_file.write("\n")
 172         # ====================================================================
 173         # ========================= Actual pinmuxing ========================#
 174         bsv_file.write('''
 175       /*====== This where the muxing starts for each io-cell======*/
 176 ''')
 177         bsv_file.write(p.pinmux)
 178         bsv_file.write('''
 179       /*============================================================*/
 180 ''')
 181         # ====================================================================
 182         # ================= interface definitions for each method =============#
 183         bsv_file.write('''
 184     interface mux_lines = interface MuxSelectionLines
 185 ''')
 186         for cell in p.muxed_cells:
 187             bsv_file.write(
 188                 mux_interface.ifacedef(
 189                     cell[0], cell_bit_width))
 190         bsv_file.write('''
 191     endinterface;
 192     interface peripheral_side = interface PeripheralSide
 193 ''')
 194         ifaces.ifacedef(bsv_file)
 195         bsv_file.write(footer)
 196         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 197         # ======================================================================
 198
 199
 200 def write_ptp(ptp, p, ifaces):
 201     with open(ptp, 'w') as bsv_file:
 202         bsv_file.write(copyright + '''
 203 package PinTop;
 204     import pinmux::*;
 205     interface Ifc_PintTop;
 206         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 207         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 208         interface PeripheralSide peripheral_side;
 209     endinterface
 210
 211     module mkPinTop(Ifc_PintTop);
 212         // instantiate the pin-mux module here
 213         Ifc_pinmux pinmux <-mkpinmux;
 214
 215         // declare the registers which will be used to mux the IOs
 216 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 217
 218         cell_bit_width = str(get_cell_bit_width(p))
 219         for cell in p.muxed_cells:
 220             bsv_file.write('''
 221                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 222                 cell_bit_width, cell[0]))
 223
 224         bsv_file.write('''
 225         // rule to connect the registers to the selection lines of the
 226         // pin-mux module
 227         rule connect_selection_registers;''')
 228
 229         for cell in p.muxed_cells:
 230             bsv_file.write('''
 231           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 232
 233         bsv_file.write('''
 234         endrule
 235         // method definitions for the write user interface
 236         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 237           Bool err=False;
 238           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 239                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 240         index = 0
 241         for cell in p.muxed_cells:
 242             bsv_file.write('''
 243             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 244             index = index + 1
 245
 246         bsv_file.write('''
 247             default: err=True;
 248           endcase
 249           return err;
 250         endmethod''')
 251
 252         bsv_file.write('''
 253         // method definitions for the read user interface
 254         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 255           Bool err=False;
 256           Bit#(32) data=0;
 257           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 258                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 259         index = 0
 260         for cell in p.muxed_cells:
 261             bsv_file.write('''
 262                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 263             index = index + 1
 264
 265         bsv_file.write('''
 266             default:err=True;
 267           endcase
 268           return tuple2(err,data);
 269         endmethod
 270         interface peripheral_side=pinmux.peripheral_side;
 271     endmodule
 272 endpackage
 273 ''')
 274
 275
 276 def write_bvp(bvp, p, ifaces):
 277     # ######## Generate bus transactors ################
 278     with open(bvp, 'w') as bsv_file:
 279         bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 280     # ##################################################