README

   1 ==========================================================================
   2 RISC-V ISA Simulator
   3 ==========================================================================
   4 # Author  : Andrew Waterman, Yunsup Lee
   5 # Date    : June 19, 2011
   6 # Version : (under version control)
   7
   8 The RISC-V ISA Simulator implements a functional model of one or more
   9 RISC-V processors.
  10
  11 --------------------------------------------------------------------------
  12 Build Steps
  13 --------------------------------------------------------------------------
  14
  15 We assume that the RISCV environment variable is set to the RISC-V tools
  16 install path, and that the riscv-fesvr package is installed there.
  17
  18  % mkdir build
  19  % cd build
  20  % ../configure --prefix=$RISCV --with-fesvr=$RISCV
  21  % make
  22  % [sudo] make install
  23
  24 --------------------------------------------------------------------------
  25 Compiling and Running a Simple C Program
  26 --------------------------------------------------------------------------
  27
  28 Install spike (see Build Steps), riscv-gcc, and riscv-pk.
  29
  30 Write a short C program and name it hello.c.  Then, compile it into a RISC-V
  31 ELF binary named hello:
  32
  33  % riscv-gcc -o hello hello.c
  34
  35 Now you can simulate the program atop the proxy kernel:
  36
  37  % spike pk hello
  38
  39 --------------------------------------------------------------------------
  40 Simulating a New Instruction
  41 --------------------------------------------------------------------------
  42
  43 Adding an instruction to the simulator requires two steps:
  44
  45   1. Describe the instruction's functional behavior in the file
  46      riscv/insns/<new_instruction_name>.h.  Examine other instructions
  47      in that directory as a starting point.
  48
  49   2. Add the opcode and opcode mask to riscv/opcodes.h.  Alternatively,
  50      add it to the riscv-opcodes package, and it will do so for you:
  51
  52       % cd ../riscv-opcodes
  53       % vi opcodes       // add a line for the new instruction
  54       % make install
  55
  56   3. Rebuild the simulator.