Set tval to 0 on traps with no specified tval
[riscv-isa-sim.git] / debug_rom / debug_rom_defines.h
1 // See LICENSE file for license details.
2
3 #ifndef DEBUG_ROM_DEFINES_H
4 #define DEBUG_ROM_DEFINES_H
5
6 // These are implementation-specific addresses in the Debug Module
7 #define DEBUG_ROM_HALTED 0x100
8 #define DEBUG_ROM_GOING 0x104
9 #define DEBUG_ROM_RESUMING 0x108
10 #define DEBUG_ROM_EXCEPTION 0x10C
11
12 // Region of memory where each hart has 1
13 // byte to read.
14 #define DEBUG_ROM_FLAGS 0x400
15 #define DEBUG_ROM_FLAG_GO 0
16 #define DEBUG_ROM_FLAG_RESUME 1
17
18 // These needs to match the link.ld
19 #define DEBUG_ROM_WHERETO 0x300
20 #define DEBUG_ROM_ENTRY 0x800
21 #define DEBUG_ROM_TVEC 0x808
22
23 #endif