Support debug system bus access.
[riscv-isa-sim.git] / dummy_rocc / dummy_rocc.cc
1 #include "rocc.h"
2 #include "mmu.h"
3 #include <cstring>
4
5 class dummy_rocc_t : public rocc_t
6 {
7 public:
8 const char* name() { return "dummy_rocc"; }
9
10 reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2)
11 {
12 reg_t prev_acc = acc[insn.rs2];
13
14 if (insn.rs2 >= num_acc)
15 illegal_instruction();
16
17 switch (insn.funct)
18 {
19 case 0: // acc <- xs1
20 acc[insn.rs2] = xs1;
21 break;
22 case 1: // xd <- acc (the only real work is the return statement below)
23 break;
24 case 2: // acc[rs2] <- Mem[xs1]
25 acc[insn.rs2] = p->get_mmu()->load_uint64(xs1);
26 break;
27 case 3: // acc[rs2] <- accX + xs1
28 acc[insn.rs2] += xs1;
29 break;
30 default:
31 illegal_instruction();
32 }
33
34 return prev_acc; // in all cases, xd <- previous value of acc[rs2]
35 }
36
37 dummy_rocc_t()
38 {
39 memset(acc, 0, sizeof(acc));
40 }
41
42 private:
43 static const int num_acc = 4;
44 reg_t acc[num_acc];
45 };
46
47 REGISTER_EXTENSION(dummy_rocc, []() { return new dummy_rocc_t; })