projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Support debug system bus access.
[riscv-isa-sim.git] / dummy_rocc / dummy_rocc.mk.in
1 dummy_rocc_subproject_deps = \
2 spike_main \
3 riscv \
4 softfloat \
5
6 dummy_rocc_srcs = \
7 dummy_rocc.cc \
Simple-V augmented version of spike