Support debug system bus access.
[riscv-isa-sim.git] / dummy_rocc / dummy_rocc_test.c
1 // The following is a RISC-V program to test the functionality of the
2 // dummy RoCC accelerator.
3 // Compile with riscv64-unknown-elf-gcc dummy_rocc_test.c
4 // Run with spike --extension=dummy_rocc pk a.out
5
6 #include <assert.h>
7 #include <stdio.h>
8 #include <stdint.h>
9
10 int main() {
11 uint64_t x = 123, y = 456, z = 0;
12 // load x into accumulator 2 (funct=0)
13 asm volatile ("custom0 x0, %0, 2, 0" : : "r"(x));
14 // read it back into z (funct=1) to verify it
15 asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z));
16 assert(z == x);
17 // accumulate 456 into it (funct=3)
18 asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y));
19 // verify it
20 asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z));
21 assert(z == x+y);
22 // do it all again, but initialize acc2 via memory this time (funct=2)
23 asm volatile ("custom0 x0, %0, 2, 2" : : "r"(&x));
24 asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y));
25 asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z));
26 assert(z == x+y);
27
28 printf("success!\n");
29 }