Use new NaN discipline
[riscv-isa-sim.git] / hwacha / hwacha.h
1 #ifndef _HWACHA_H
2 #define _HWACHA_H
3
4 #include "extension.h"
5
6 struct ct_state_t
7 {
8 void reset();
9
10 uint32_t nxpr;
11 uint32_t nfpr;
12 uint32_t maxvl;
13 uint32_t vl;
14 uint32_t count;
15 uint32_t prec;
16
17 reg_t vf_pc;
18 };
19
20 struct ut_state_t
21 {
22 void reset();
23
24 bool run;
25 regfile_t<reg_t, 32, true> XPR;
26 regfile_t<reg_t, 32, false> FPR;
27 };
28
29 class hwacha_t : public extension_t
30 {
31 public:
32 hwacha_t() : cause(0), aux(0), debug(false) {}
33 std::vector<insn_desc_t> get_instructions();
34 std::vector<disasm_insn_t*> get_disasms();
35 const char* name() { return "hwacha"; }
36 void reset();
37 void set_debug(bool value) { debug = value; }
38
39 ct_state_t* get_ct_state() { return &ct_state; }
40 ut_state_t* get_ut_state(int idx) { return &ut_state[idx]; }
41 bool vf_active();
42 reg_t get_cause() { return cause; }
43 reg_t get_aux() { return aux; }
44 void take_exception(reg_t, reg_t);
45 void clear_exception() { clear_interrupt(); }
46
47 bool get_debug() { return debug; }
48 disassembler_t* get_ut_disassembler() { return &ut_disassembler; }
49
50 static const int max_uts = 2048;
51
52 private:
53 ct_state_t ct_state;
54 ut_state_t ut_state[max_uts];
55 reg_t cause;
56 reg_t aux;
57
58 disassembler_t ut_disassembler;
59 bool debug;
60 };
61
62 #endif