3 WRITE_VF_PC(XS1
+ insn
.s_imm());
4 for (uint32_t i
=0; i
<VL
; i
++)
5 h
->get_ut_state(i
)->run
= true;
11 h
->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH
, VF_PC
);
13 insn_t ut_insn
= p
->get_mmu()->load_insn(VF_PC
).insn
;
17 #define DECLARE_INSN(name, match, mask) \
18 extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
19 if ((ut_insn.bits() & mask) == match) { \
20 WRITE_VF_PC(hwacha_##name(p, ut_insn, VF_PC)); \
23 #include "opcodes_hwacha_ut.h"
27 h
->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION
, VF_PC
);
29 if (!h
->get_debug()) {
33 fprintf(stderr
, "vf block: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
34 VF_PC
, ut_insn
.bits(), h
->get_ut_disassembler()->disassemble(ut_insn
).c_str());