Use new NaN discipline
[riscv-isa-sim.git] / hwacha / insns / vf.h
1 if (VL) {
2 if (!h->vf_active()) {
3 WRITE_VF_PC(XS1 + insn.s_imm());
4 for (uint32_t i=0; i<VL; i++)
5 h->get_ut_state(i)->run = true;
6 }
7
8 vf_loop:
9
10 if (VF_PC & 3)
11 h->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH, VF_PC);
12
13 insn_t ut_insn = p->get_mmu()->load_insn(VF_PC).insn;
14
15 bool matched = false;
16
17 #define DECLARE_INSN(name, match, mask) \
18 extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
19 if ((ut_insn.bits() & mask) == match) { \
20 WRITE_VF_PC(hwacha_##name(p, ut_insn, VF_PC)); \
21 matched = true; \
22 }
23 #include "opcodes_hwacha_ut.h"
24 #undef DECLARE_INSN
25
26 if (!matched)
27 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION, VF_PC);
28
29 if (!h->get_debug()) {
30 if (h->vf_active())
31 goto vf_loop;
32 } else {
33 fprintf(stderr, "vf block: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
34 VF_PC, ut_insn.bits(), h->get_ut_disassembler()->disassemble(ut_insn).c_str());
35 if (h->vf_active())
36 npc = pc;
37 }
38 }