Use new NaN discipline
[riscv-isa-sim.git] / hwacha / insns / vsetcfg.h
1 uint32_t nxpr = (XS1 & 0x3f) + (insn.i_imm() & 0x3f);
2 uint32_t nfpr = ((XS1 >> 6) & 0x3f) + ((insn.i_imm() >> 6) & 0x3f);
3 if (nxpr > 32)
4 h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 0);
5 if (nfpr > 32)
6 h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 1);
7 WRITE_NXPR(nxpr);
8 WRITE_NFPR(nfpr);
9 uint32_t maxvl;
10 if (nxpr + nfpr < 2)
11 maxvl = 8 * 256;
12 else
13 maxvl = 8 * (256 / (nxpr-1 + nfpr));
14 WRITE_MAXVL(maxvl);
15 WRITE_VL(0);