Use new NaN discipline
[riscv-isa-sim.git] / hwacha / insns / vxcpthold.h
1 require_supervisor_hwacha;
2 reg_t addr = XS1;
3
4 #define LOAD_B(addr) \
5 (addr += 1, p->get_mmu()->load_uint8(addr-1))
6
7 #define LOAD_W(addr) \
8 (addr += 4, p->get_mmu()->load_uint32(addr-4))
9
10 #define LOAD_D(addr) \
11 (addr += 8, p->get_mmu()->load_uint64(addr-8))
12
13 // to be compliant with the evac structure
14 addr += 8;
15
16 WRITE_NXPR(LOAD_W(addr));
17 WRITE_NFPR(LOAD_W(addr));
18 WRITE_MAXVL(LOAD_W(addr));
19 WRITE_VL(LOAD_W(addr));
20 WRITE_UTIDX(LOAD_W(addr));
21 WRITE_PREC(LOAD_W(addr));
22 WRITE_VF_PC(LOAD_D(addr));
23
24 for (uint32_t x=1; x<NXPR; x++) {
25 for (uint32_t i=0; i<VL; i++) {
26 UT_WRITE_XPR(i, x, LOAD_D(addr));
27 }
28 }
29
30 for (uint32_t f=0; f<NFPR; f++) {
31 for (uint32_t i=0; i<VL; i++) {
32 UT_WRITE_FPR(i, f, LOAD_D(addr));
33 }
34 }
35
36 for (uint32_t i=0; i<VL; i++) {
37 h->get_ut_state(i)->run = LOAD_B(addr);
38 }
39
40 #undef LOAD_B
41 #undef LOAD_W
42 #undef LOAD_D