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HEAD
Use new NaN discipline
[riscv-isa-sim.git]
/
hwacha
/
insns_ut
/
ut_fcvt_l_h.h
1
require_rv64
;
2
require_fp
;
3
softfloat_roundingMode
=
RM
;
4
WRITE_RD
(
f32_to_i64
(
HFRS1
,
RM
,
true
));
5
set_fp_exceptions
;