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Use new NaN discipline
[riscv-isa-sim.git] / hwacha / insns_ut / ut_fsgnj_h.h
1 require_fp;
2 WRITE_FRD((FRS1 &~ (uint16_t)INT16_MIN) | (FRS2 & (uint16_t)INT16_MIN));
Simple-V augmented version of spike