riscv/debug_defines.h

   1 #define DTM_IDCODE                          0x01
   2 /*
   3 * Identifies the release version of this part.
   4  */
   5 #define DTM_IDCODE_VERSION_OFFSET           28
   6 #define DTM_IDCODE_VERSION_LENGTH           4
   7 #define DTM_IDCODE_VERSION                  (0xf << DTM_IDCODE_VERSION_OFFSET)
   8 /*
   9 * Identifies the designer's part number of this part.
  10  */
  11 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
  12 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
  13 #define DTM_IDCODE_PARTNUMBER               (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET)
  14 /*
  15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
  16 * bits 6:0 of the designer/manufacturer's Identification Code as
  17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
  18 * count of the number of continuation characters (0x7f) in that same
  19 * Identification Code.
  20  */
  21 #define DTM_IDCODE_MANUFID_OFFSET           1
  22 #define DTM_IDCODE_MANUFID_LENGTH           11
  23 #define DTM_IDCODE_MANUFID                  (0x7ff << DTM_IDCODE_MANUFID_OFFSET)
  24 #define DTM_IDCODE_1_OFFSET                 0
  25 #define DTM_IDCODE_1_LENGTH                 1
  26 #define DTM_IDCODE_1                        (0x1 << DTM_IDCODE_1_OFFSET)
  27 #define DTM_DTMCS                           0x10
  28 /*
  29 * Writing 1 to this bit does a hard reset of the DTM,
  30 * causing the DTM to forget about any outstanding DMI transactions.
  31 * In general this should only be used when the Debugger has
  32 * reason to expect that the outstanding DMI transaction will never
  33 * complete (e.g. a reset condition caused an inflight DMI transaction to
  34 * be cancelled).
  35  */
  36 #define DTM_DTMCS_DMIHARDRESET_OFFSET       17
  37 #define DTM_DTMCS_DMIHARDRESET_LENGTH       1
  38 #define DTM_DTMCS_DMIHARDRESET              (0x1 << DTM_DTMCS_DMIHARDRESET_OFFSET)
  39 /*
  40 * Writing 1 to this bit clears the sticky error state
  41 * and allows the DTM to retry or complete the previous
  42 * transaction.
  43  */
  44 #define DTM_DTMCS_DMIRESET_OFFSET           16
  45 #define DTM_DTMCS_DMIRESET_LENGTH           1
  46 #define DTM_DTMCS_DMIRESET                  (0x1 << DTM_DTMCS_DMIRESET_OFFSET)
  47 /*
  48 * This is a hint to the debugger of the minimum number of
  49 * cycles a debugger should spend in
  50 * Run-Test/Idle after every DMI scan to avoid a `busy'
  51 * return code (\Fdmistat of 3). A debugger must still
  52 * check \Fdmistat when necessary.
  53 *
  54 * 0: It is not necessary to enter Run-Test/Idle at all.
  55 *
  56 * 1: Enter Run-Test/Idle and leave it immediately.
  57 *
  58 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
  59 *
  60 * And so on.
  61  */
  62 #define DTM_DTMCS_IDLE_OFFSET               12
  63 #define DTM_DTMCS_IDLE_LENGTH               3
  64 #define DTM_DTMCS_IDLE                      (0x7 << DTM_DTMCS_IDLE_OFFSET)
  65 /*
  66 * 0: No error.
  67 *
  68 * 1: Reserved. Interpret the same as 2.
  69 *
  70 * 2: An operation failed (resulted in \Fop of 2).
  71 *
  72 * 3: An operation was attempted while a DMI access was still in
  73 * progress (resulted in \Fop of 3).
  74  */
  75 #define DTM_DTMCS_DMISTAT_OFFSET            10
  76 #define DTM_DTMCS_DMISTAT_LENGTH            2
  77 #define DTM_DTMCS_DMISTAT                   (0x3 << DTM_DTMCS_DMISTAT_OFFSET)
  78 /*
  79 * The size of \Faddress in \Rdmi.
  80  */
  81 #define DTM_DTMCS_ABITS_OFFSET              4
  82 #define DTM_DTMCS_ABITS_LENGTH              6
  83 #define DTM_DTMCS_ABITS                     (0x3f << DTM_DTMCS_ABITS_OFFSET)
  84 /*
  85 * 0: Version described in spec version 0.11.
  86 *
  87 * 1: Version described in spec version 0.12 (and later?), which
  88 * reduces the DMI data width to 32 bits.
  89 *
  90 * Other values are reserved for future use.
  91  */
  92 #define DTM_DTMCS_VERSION_OFFSET            0
  93 #define DTM_DTMCS_VERSION_LENGTH            4
  94 #define DTM_DTMCS_VERSION                   (0xf << DTM_DTMCS_VERSION_OFFSET)
  95 #define DTM_DMI                             0x11
  96 /*
  97 * Address used for DMI access. In Update-DR this value is used
  98 * to access the DM over the DMI.
  99  */
 100 #define DTM_DMI_ADDRESS_OFFSET              34
 101 #define DTM_DMI_ADDRESS_LENGTH              abits
 102 #define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
 103 /*
 104 * The data to send to the DM over the DMI during Update-DR, and
 105 * the data returned from the DM as a result of the previous operation.
 106  */
 107 #define DTM_DMI_DATA_OFFSET                 2
 108 #define DTM_DMI_DATA_LENGTH                 32
 109 #define DTM_DMI_DATA                        (0xffffffffL << DTM_DMI_DATA_OFFSET)
 110 /*
 111 * When the debugger writes this field, it has the following meaning:
 112 *
 113 * 0: Ignore \Fdata. (nop)
 114 *
 115 * 1: Read from \Faddress. (read)
 116 *
 117 * 2: Write \Fdata to \Faddress. (write)
 118 *
 119 * 3: Reserved.
 120 *
 121 * When the debugger reads this field, it means the following:
 122 *
 123 * 0: The previous operation completed successfully.
 124 *
 125 * 1: Reserved.
 126 *
 127 * 2: A previous operation failed.  The data scanned into \Rdmi in
 128 * this access will be ignored.  This status is sticky and can be
 129 * cleared by writing \Fdmireset in \Rdtmcs.
 130 *
 131 * This indicates that the DM itself responded with an error, e.g.
 132 * in the System Bus and Serial Port overflow/underflow cases.
 133 *
 134 * 3: An operation was attempted while a DMI request is still in
 135 * progress. The data scanned into \Rdmi in this access will be
 136 * ignored. This status is sticky and can be cleared by writing
 137 * \Fdmireset in \Rdtmcs. If a debugger sees this status, it
 138 * needs to give the target more TCK edges between Update-DR and
 139 * Capture-DR. The simplest way to do that is to add extra transitions
 140 * in Run-Test/Idle.
 141 *
 142 * (The DTM, DM, and/or component may be in different clock domains,
 143 * so synchronization may be required. Some relatively fixed number of
 144 * TCK ticks may be needed for the request to reach the DM, complete,
 145 * and for the response to be synchronized back into the TCK domain.)
 146  */
 147 #define DTM_DMI_OP_OFFSET                   0
 148 #define DTM_DMI_OP_LENGTH                   2
 149 #define DTM_DMI_OP                          (0x3L << DTM_DMI_OP_OFFSET)
 150 #define CSR_DCSR                            0x7b0
 151 /*
 152 * 0: There is no external debug support.
 153 *
 154 * 1: External debug support exists as it is described in this document.
 155 *
 156 * Other values are reserved for future standards.
 157  */
 158 #define CSR_DCSR_XDEBUGVER_OFFSET           30
 159 #define CSR_DCSR_XDEBUGVER_LENGTH           2
 160 #define CSR_DCSR_XDEBUGVER                  (0x3 << CSR_DCSR_XDEBUGVER_OFFSET)
 161 /*
 162 * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode.
 163  */
 164 #define CSR_DCSR_EBREAKM_OFFSET             15
 165 #define CSR_DCSR_EBREAKM_LENGTH             1
 166 #define CSR_DCSR_EBREAKM                    (0x1 << CSR_DCSR_EBREAKM_OFFSET)
 167 /*
 168 * When 1, {\tt ebreak} instructions in Hypervisor Mode enter Debug Mode.
 169  */
 170 #define CSR_DCSR_EBREAKH_OFFSET             14
 171 #define CSR_DCSR_EBREAKH_LENGTH             1
 172 #define CSR_DCSR_EBREAKH                    (0x1 << CSR_DCSR_EBREAKH_OFFSET)
 173 /*
 174 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode.
 175  */
 176 #define CSR_DCSR_EBREAKS_OFFSET             13
 177 #define CSR_DCSR_EBREAKS_LENGTH             1
 178 #define CSR_DCSR_EBREAKS                    (0x1 << CSR_DCSR_EBREAKS_OFFSET)
 179 /*
 180 * When 1, {\tt ebreak} instructions in User/Application Mode enter
 181 * Debug Mode.
 182  */
 183 #define CSR_DCSR_EBREAKU_OFFSET             12
 184 #define CSR_DCSR_EBREAKU_LENGTH             1
 185 #define CSR_DCSR_EBREAKU                    (0x1 << CSR_DCSR_EBREAKU_OFFSET)
 186 /*
 187 * 0: Increment counters as usual.
 188 *
 189 * 1: Don't increment any counters while in Debug Mode.  This includes
 190 * the {\tt cycle} and {\tt instret} CSRs. This is preferred for most
 191 * debugging scenarios.
 192 *
 193 * An implementation may choose not to support writing to this bit.
 194 * The debugger must read back the value it writes to check whether
 195 * the feature is supported.
 196  */
 197 #define CSR_DCSR_STOPCOUNT_OFFSET           10
 198 #define CSR_DCSR_STOPCOUNT_LENGTH           1
 199 #define CSR_DCSR_STOPCOUNT                  (0x1 << CSR_DCSR_STOPCOUNT_OFFSET)
 200 /*
 201 * 0: Increment timers as usual.
 202 *
 203 * 1: Don't increment any hart-local timers while in Debug Mode.
 204 *
 205 * An implementation may choose not to support writing to this bit.
 206 * The debugger must read back the value it writes to check whether
 207 * the feature is supported.
 208  */
 209 #define CSR_DCSR_STOPTIME_OFFSET            9
 210 #define CSR_DCSR_STOPTIME_LENGTH            1
 211 #define CSR_DCSR_STOPTIME                   (0x1 << CSR_DCSR_STOPTIME_OFFSET)
 212 /*
 213 * Explains why Debug Mode was entered.
 214 *
 215 * When there are multiple reasons to enter Debug Mode in a single
 216 * cycle, the cause with the highest priority is the one written.
 217 *
 218 * 1: An {\tt ebreak} instruction was executed. (priority 3)
 219 *
 220 * 2: The Trigger Module caused a halt. (priority 4)
 221 *
 222 * 3: \Fhaltreq was set. (priority 2)
 223 *
 224 * 4: The hart single stepped because \Fstep was set. (priority 1)
 225 *
 226 * Other values are reserved for future use.
 227  */
 228 #define CSR_DCSR_CAUSE_OFFSET               6
 229 #define CSR_DCSR_CAUSE_LENGTH               3
 230 #define CSR_DCSR_CAUSE                      (0x7 << CSR_DCSR_CAUSE_OFFSET)
 231 /*
 232 * When set and not in Debug Mode, the hart will only execute a single
 233 * instruction and then enter Debug Mode.
 234 * Interrupts are disabled when this bit is set.
 235 * If the instruction does not complete due to an exception,
 236 * the hart will immediately enter Debug Mode before executing
 237 * the trap handler, with appropriate exception registers set.
 238  */
 239 #define CSR_DCSR_STEP_OFFSET                2
 240 #define CSR_DCSR_STEP_LENGTH                1
 241 #define CSR_DCSR_STEP                       (0x1 << CSR_DCSR_STEP_OFFSET)
 242 /*
 243 * Contains the privilege level the hart was operating in when Debug
 244 * Mode was entered. The encoding is described in Table
 245 * \ref{tab:privlevel}.  A debugger can change this value to change
 246 * the hart's privilege level when exiting Debug Mode.
 247 *
 248 * Not all privilege levels are supported on all harts. If the
 249 * encoding written is not supported or the debugger is not allowed to
 250 * change to it, the hart may change to any supported privilege level.
 251  */
 252 #define CSR_DCSR_PRV_OFFSET                 0
 253 #define CSR_DCSR_PRV_LENGTH                 2
 254 #define CSR_DCSR_PRV                        (0x3 << CSR_DCSR_PRV_OFFSET)
 255 #define CSR_DPC                             0x7b1
 256 #define CSR_DPC_DPC_OFFSET                  0
 257 #define CSR_DPC_DPC_LENGTH                  XLEN
 258 #define CSR_DPC_DPC                         (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
 259 #define CSR_DSCRATCH0                       0x7b2
 260 #define CSR_DSCRATCH1                       0x7b3
 261 #define CSR_PRIV                            virtual
 262 /*
 263 * Contains the privilege level the hart was operating in when Debug
 264 * Mode was entered. The encoding is described in Table
 265 * \ref{tab:privlevel}. A user can write this value to change the
 266 * hart's privilege level when exiting Debug Mode.
 267  */
 268 #define CSR_PRIV_PRV_OFFSET                 0
 269 #define CSR_PRIV_PRV_LENGTH                 2
 270 #define CSR_PRIV_PRV                        (0x3 << CSR_PRIV_PRV_OFFSET)
 271 #define CSR_TSELECT                         0x7a0
 272 #define CSR_TSELECT_INDEX_OFFSET            0
 273 #define CSR_TSELECT_INDEX_LENGTH            XLEN
 274 #define CSR_TSELECT_INDEX                   (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
 275 #define CSR_TDATA1                          0x7a1
 276 /*
 277 * 0: There is no trigger at this \Rtselect.
 278 *
 279 * 1: The trigger is a legacy SiFive address match trigger. These
 280 * should not be implemented and aren't further documented here.
 281 *
 282 * 2: The trigger is an address/data match trigger. The remaining bits
 283 * in this register act as described in \Rmcontrol.
 284 *
 285 * 3: The trigger is an instruction count trigger. The remaining bits
 286 * in this register act as described in \Ricount.
 287 *
 288 * 15: This trigger exists (so enumeration shouldn't terminate), but
 289 * is not currently available.
 290 *
 291 * Other values are reserved for future use.
 292  */
 293 #define CSR_TDATA1_TYPE_OFFSET              XLEN-4
 294 #define CSR_TDATA1_TYPE_LENGTH              4
 295 #define CSR_TDATA1_TYPE                     (0xfL << CSR_TDATA1_TYPE_OFFSET)
 296 /*
 297 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the
 298 * selected \Rtselect.
 299 *
 300 * 1: Only Debug Mode can write the {\tt tdata} registers at the
 301 * selected \Rtselect.  Writes from other modes are ignored.
 302 *
 303 * This bit is only writable from Debug Mode.
 304  */
 305 #define CSR_TDATA1_HMODE_OFFSET             XLEN-5
 306 #define CSR_TDATA1_HMODE_LENGTH             1
 307 #define CSR_TDATA1_HMODE                    (0x1L << CSR_TDATA1_HMODE_OFFSET)
 308 /*
 309 * Trigger-specific data.
 310  */
 311 #define CSR_TDATA1_DATA_OFFSET              0
 312 #define CSR_TDATA1_DATA_LENGTH              XLEN - 5
 313 #define CSR_TDATA1_DATA                     (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
 314 #define CSR_TDATA2                          0x7a2
 315 #define CSR_TDATA2_DATA_OFFSET              0
 316 #define CSR_TDATA2_DATA_LENGTH              XLEN
 317 #define CSR_TDATA2_DATA                     (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET)
 318 #define CSR_TDATA3                          0x7a3
 319 #define CSR_TDATA3_DATA_OFFSET              0
 320 #define CSR_TDATA3_DATA_LENGTH              XLEN
 321 #define CSR_TDATA3_DATA                     (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET)
 322 #define CSR_MCONTROL                        0x7a1
 323 #define CSR_MCONTROL_TYPE_OFFSET            XLEN-4
 324 #define CSR_MCONTROL_TYPE_LENGTH            4
 325 #define CSR_MCONTROL_TYPE                   (0xfL << CSR_MCONTROL_TYPE_OFFSET)
 326 #define CSR_MCONTROL_DMODE_OFFSET           XLEN-5
 327 #define CSR_MCONTROL_DMODE_LENGTH           1
 328 #define CSR_MCONTROL_DMODE                  (0x1L << CSR_MCONTROL_DMODE_OFFSET)
 329 /*
 330 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
 331 * supported by the hardware. The value is the logarithm base 2 of the
 332 * number of bytes in that range.  A value of 0 indicates that only
 333 * exact value matches are supported (one byte range). A value of 63
 334 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
 335 * size.
 336  */
 337 #define CSR_MCONTROL_MASKMAX_OFFSET         XLEN-11
 338 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 339 #define CSR_MCONTROL_MASKMAX                (0x3fL << CSR_MCONTROL_MASKMAX_OFFSET)
 340 /*
 341 * 0: Perform a match on the virtual address.
 342 *
 343 * 1: Perform a match on the data value loaded/stored, or the
 344 * instruction executed.
 345  */
 346 #define CSR_MCONTROL_SELECT_OFFSET          19
 347 #define CSR_MCONTROL_SELECT_LENGTH          1
 348 #define CSR_MCONTROL_SELECT                 (0x1L << CSR_MCONTROL_SELECT_OFFSET)
 349 /*
 350 * 0: The action for this trigger will be taken just before the
 351 * instruction that triggered it is executed, but after all preceding
 352 * instructions are are committed.
 353 *
 354 * 1: The action for this trigger will be taken after the instruction
 355 * that triggered it is executed. It should be taken before the next
 356 * instruction is executed, but it is better to implement triggers and
 357 * not implement that suggestion than to not implement them at all.
 358 *
 359 * Most hardware will only implement one timing or the other, possibly
 360 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
 361 * primarily exists for the hardware to communicate to the debugger
 362 * what will happen. Hardware may implement the bit fully writable, in
 363 * which case the debugger has a little more control.
 364 *
 365 * Data load triggers with \Ftiming of 0 will result in the same load
 366 * happening again when the debugger lets the core run. For data load
 367 * triggers, debuggers must first attempt to set the breakpoint with
 368 * \Ftiming of 1.
 369 *
 370 * A chain of triggers that don't all have the same \Ftiming value
 371 * will never fire (unless consecutive instructions match the
 372 * appropriate triggers).
 373  */
 374 #define CSR_MCONTROL_TIMING_OFFSET          18
 375 #define CSR_MCONTROL_TIMING_LENGTH          1
 376 #define CSR_MCONTROL_TIMING                 (0x1L << CSR_MCONTROL_TIMING_OFFSET)
 377 /*
 378 * Determines what happens when this trigger matches.
 379 *
 380 * 0: Raise a breakpoint exception. (Used when software wants to use
 381 * the trigger module without an external debugger attached.)
 382 *
 383 * 1: Enter Debug Mode. (Only supported when \Fhmode is 1.)
 384 *
 385 * 2: Start tracing.
 386 *
 387 * 3: Stop tracing.
 388 *
 389 * 4: Emit trace data for this match. If it is a data access match,
 390 * emit appropriate Load/Store Address/Data. If it is an instruction
 391 * execution, emit its PC.
 392 *
 393 * Other values are reserved for future use.
 394  */
 395 #define CSR_MCONTROL_ACTION_OFFSET          12
 396 #define CSR_MCONTROL_ACTION_LENGTH          6
 397 #define CSR_MCONTROL_ACTION                 (0x3fL << CSR_MCONTROL_ACTION_OFFSET)
 398 /*
 399 * 0: When this trigger matches, the configured action is taken.
 400 *
 401 * 1: While this trigger does not match, it prevents the trigger with
 402 * the next index from matching.
 403  */
 404 #define CSR_MCONTROL_CHAIN_OFFSET           11
 405 #define CSR_MCONTROL_CHAIN_LENGTH           1
 406 #define CSR_MCONTROL_CHAIN                  (0x1L << CSR_MCONTROL_CHAIN_OFFSET)
 407 /*
 408 * 0: Matches when the value equals \Rtdatatwo.
 409 *
 410 * 1: Matches when the top M bits of the value match the top M bits of
 411 * \Rtdatatwo. M is XLEN-1 minus the index of the least-significant
 412 * bit containing 0 in \Rtdatatwo.
 413 *
 414 * 2: Matches when the value is greater than or equal to \Rtdatatwo.
 415 *
 416 * 3: Matches when the value is less than \Rtdatatwo.
 417 *
 418 * 4: Matches when the lower half of the value equals the lower half
 419 * of \Rtdatatwo after the lower half of the value is ANDed with the
 420 * upper half of \Rtdatatwo.
 421 *
 422 * 5: Matches when the upper half of the value equals the lower half
 423 * of \Rtdatatwo after the upper half of the value is ANDed with the
 424 * upper half of \Rtdatatwo.
 425 *
 426 * Other values are reserved for future use.
 427  */
 428 #define CSR_MCONTROL_MATCH_OFFSET           7
 429 #define CSR_MCONTROL_MATCH_LENGTH           4
 430 #define CSR_MCONTROL_MATCH                  (0xfL << CSR_MCONTROL_MATCH_OFFSET)
 431 /*
 432 * When set, enable this trigger in M mode.
 433  */
 434 #define CSR_MCONTROL_M_OFFSET               6
 435 #define CSR_MCONTROL_M_LENGTH               1
 436 #define CSR_MCONTROL_M                      (0x1L << CSR_MCONTROL_M_OFFSET)
 437 /*
 438 * When set, enable this trigger in H mode.
 439  */
 440 #define CSR_MCONTROL_H_OFFSET               5
 441 #define CSR_MCONTROL_H_LENGTH               1
 442 #define CSR_MCONTROL_H                      (0x1L << CSR_MCONTROL_H_OFFSET)
 443 /*
 444 * When set, enable this trigger in S mode.
 445  */
 446 #define CSR_MCONTROL_S_OFFSET               4
 447 #define CSR_MCONTROL_S_LENGTH               1
 448 #define CSR_MCONTROL_S                      (0x1L << CSR_MCONTROL_S_OFFSET)
 449 /*
 450 * When set, enable this trigger in U mode.
 451  */
 452 #define CSR_MCONTROL_U_OFFSET               3
 453 #define CSR_MCONTROL_U_LENGTH               1
 454 #define CSR_MCONTROL_U                      (0x1L << CSR_MCONTROL_U_OFFSET)
 455 /*
 456 * When set, the trigger fires on the virtual address or opcode of an
 457 * instruction that is executed.
 458  */
 459 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 460 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 461 #define CSR_MCONTROL_EXECUTE                (0x1L << CSR_MCONTROL_EXECUTE_OFFSET)
 462 /*
 463 * When set, the trigger fires on the virtual address or data of a store.
 464  */
 465 #define CSR_MCONTROL_STORE_OFFSET           1
 466 #define CSR_MCONTROL_STORE_LENGTH           1
 467 #define CSR_MCONTROL_STORE                  (0x1L << CSR_MCONTROL_STORE_OFFSET)
 468 /*
 469 * When set, the trigger fires on the virtual address or data of a load.
 470  */
 471 #define CSR_MCONTROL_LOAD_OFFSET            0
 472 #define CSR_MCONTROL_LOAD_LENGTH            1
 473 #define CSR_MCONTROL_LOAD                   (0x1L << CSR_MCONTROL_LOAD_OFFSET)
 474 #define CSR_ICOUNT                          0x7a1
 475 #define CSR_ICOUNT_TYPE_OFFSET              XLEN-4
 476 #define CSR_ICOUNT_TYPE_LENGTH              4
 477 #define CSR_ICOUNT_TYPE                     (0xfL << CSR_ICOUNT_TYPE_OFFSET)
 478 #define CSR_ICOUNT_DMODE_OFFSET             XLEN-5
 479 #define CSR_ICOUNT_DMODE_LENGTH             1
 480 #define CSR_ICOUNT_DMODE                    (0x1L << CSR_ICOUNT_DMODE_OFFSET)
 481 /*
 482 * When count is decremented to 0, the trigger fires. Instead of
 483 * changing \Fcount from 1 to 0, it is also acceptable for hardware to
 484 * clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired
 485 * to 1 if this register just exists for single step.
 486  */
 487 #define CSR_ICOUNT_COUNT_OFFSET             10
 488 #define CSR_ICOUNT_COUNT_LENGTH             14
 489 #define CSR_ICOUNT_COUNT                    (0x3fffL << CSR_ICOUNT_COUNT_OFFSET)
 490 /*
 491 * When set, every instruction completed or exception taken in M mode decrements \Fcount
 492 * by 1.
 493  */
 494 #define CSR_ICOUNT_M_OFFSET                 9
 495 #define CSR_ICOUNT_M_LENGTH                 1
 496 #define CSR_ICOUNT_M                        (0x1L << CSR_ICOUNT_M_OFFSET)
 497 /*
 498 * When set, every instruction completed or exception taken in in H mode decrements \Fcount
 499 * by 1.
 500  */
 501 #define CSR_ICOUNT_H_OFFSET                 8
 502 #define CSR_ICOUNT_H_LENGTH                 1
 503 #define CSR_ICOUNT_H                        (0x1L << CSR_ICOUNT_H_OFFSET)
 504 /*
 505 * When set, every instruction completed or exception taken in S mode decrements \Fcount
 506 * by 1.
 507  */
 508 #define CSR_ICOUNT_S_OFFSET                 7
 509 #define CSR_ICOUNT_S_LENGTH                 1
 510 #define CSR_ICOUNT_S                        (0x1L << CSR_ICOUNT_S_OFFSET)
 511 /*
 512 * When set, every instruction completed or exception taken in U mode decrements \Fcount
 513 * by 1.
 514  */
 515 #define CSR_ICOUNT_U_OFFSET                 6
 516 #define CSR_ICOUNT_U_LENGTH                 1
 517 #define CSR_ICOUNT_U                        (0x1L << CSR_ICOUNT_U_OFFSET)
 518 /*
 519 * Determines what happens when this trigger matches.
 520 *
 521 * 0: Raise a breakpoint exception. (Used when software wants to use the
 522 * trigger module without an external debugger attached.)
 523 *
 524 * 1: Enter Debug Mode. (Only supported when \Fhmode is 1.)
 525 *
 526 * 2: Start tracing.
 527 *
 528 * 3: Stop tracing.
 529 *
 530 * 4: Emit trace data for this match. If it is a data access match,
 531 * emit appropriate Load/Store Address/Data. If it is an instruction
 532 * execution, emit its PC.
 533 *
 534 * Other values are reserved for future use.
 535  */
 536 #define CSR_ICOUNT_ACTION_OFFSET            0
 537 #define CSR_ICOUNT_ACTION_LENGTH            6
 538 #define CSR_ICOUNT_ACTION                   (0x3fL << CSR_ICOUNT_ACTION_OFFSET)
 539 #define DMI_DMSTATUS                        0x11
 540 /*
 541 * This field is 1 when all currently selected harts have acknowledged the previous \Fresumereq.
 542  */
 543 #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET    17
 544 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH    1
 545 #define DMI_DMSTATUS_ALLRESUMEACK           (0x1 << DMI_DMSTATUS_ALLRESUMEACK_OFFSET)
 546 /*
 547 * This field is 1 when any currently selected hart has acknowledged the previous \Fresumereq.
 548  */
 549 #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET    16
 550 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH    1
 551 #define DMI_DMSTATUS_ANYRESUMEACK           (0x1 << DMI_DMSTATUS_ANYRESUMEACK_OFFSET)
 552 /*
 553 * This field is 1 when all currently selected harts do not exist in this system.
 554  */
 555 #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET  15
 556 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH  1
 557 #define DMI_DMSTATUS_ALLNONEXISTENT         (0x1 << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET)
 558 /*
 559 * This field is 1 when any currently selected hart does not exist in this system.
 560  */
 561 #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET  14
 562 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH  1
 563 #define DMI_DMSTATUS_ANYNONEXISTENT         (0x1 << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET)
 564 /*
 565 * This field is 1 when all currently selected harts are unavailable.
 566  */
 567 #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET      13
 568 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH      1
 569 #define DMI_DMSTATUS_ALLUNAVAIL             (0x1 << DMI_DMSTATUS_ALLUNAVAIL_OFFSET)
 570 /*
 571 * This field is 1 when any currently selected hart is unavailable.
 572  */
 573 #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET      12
 574 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH      1
 575 #define DMI_DMSTATUS_ANYUNAVAIL             (0x1 << DMI_DMSTATUS_ANYUNAVAIL_OFFSET)
 576 /*
 577 * This field is 1 when all currently selected harts are running.
 578  */
 579 #define DMI_DMSTATUS_ALLRUNNING_OFFSET      11
 580 #define DMI_DMSTATUS_ALLRUNNING_LENGTH      1
 581 #define DMI_DMSTATUS_ALLRUNNING             (0x1 << DMI_DMSTATUS_ALLRUNNING_OFFSET)
 582 /*
 583 * This field is 1 when any currently selected hart is running.
 584  */
 585 #define DMI_DMSTATUS_ANYRUNNING_OFFSET      10
 586 #define DMI_DMSTATUS_ANYRUNNING_LENGTH      1
 587 #define DMI_DMSTATUS_ANYRUNNING             (0x1 << DMI_DMSTATUS_ANYRUNNING_OFFSET)
 588 /*
 589 * This field is 1 when all currently selected harts are halted.
 590  */
 591 #define DMI_DMSTATUS_ALLHALTED_OFFSET       9
 592 #define DMI_DMSTATUS_ALLHALTED_LENGTH       1
 593 #define DMI_DMSTATUS_ALLHALTED              (0x1 << DMI_DMSTATUS_ALLHALTED_OFFSET)
 594 /*
 595 * This field is 1 when any currently selected hart is halted.
 596  */
 597 #define DMI_DMSTATUS_ANYHALTED_OFFSET       8
 598 #define DMI_DMSTATUS_ANYHALTED_LENGTH       1
 599 #define DMI_DMSTATUS_ANYHALTED              (0x1 << DMI_DMSTATUS_ANYHALTED_OFFSET)
 600 /*
 601 * 0 when authentication is required before using the DM.  1 when the
 602 * authentication check has passed. On components that don't implement
 603 * authentication, this bit must be preset as 1.
 604  */
 605 #define DMI_DMSTATUS_AUTHENTICATED_OFFSET   7
 606 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH   1
 607 #define DMI_DMSTATUS_AUTHENTICATED          (0x1 << DMI_DMSTATUS_AUTHENTICATED_OFFSET)
 608 /*
 609 * 0: The authentication module is ready to process the next
 610 * read/write to \Rauthdata.
 611 *
 612 * 1: The authentication module is busy. Accessing \Rauthdata results
 613 * in unspecified behavior.
 614 *
 615 * \Fauthbusy only becomes set in immediate response to an access to
 616 * \Rauthdata.
 617  */
 618 #define DMI_DMSTATUS_AUTHBUSY_OFFSET        6
 619 #define DMI_DMSTATUS_AUTHBUSY_LENGTH        1
 620 #define DMI_DMSTATUS_AUTHBUSY               (0x1 << DMI_DMSTATUS_AUTHBUSY_OFFSET)
 621 #define DMI_DMSTATUS_CFGSTRVALID_OFFSET     4
 622 #define DMI_DMSTATUS_CFGSTRVALID_LENGTH     1
 623 #define DMI_DMSTATUS_CFGSTRVALID            (0x1 << DMI_DMSTATUS_CFGSTRVALID_OFFSET)
 624 /*
 625 * Reserved for future use. Reads as 0.
 626  */
 627 #define DMI_DMSTATUS_VERSIONHI_OFFSET       2
 628 #define DMI_DMSTATUS_VERSIONHI_LENGTH       2
 629 #define DMI_DMSTATUS_VERSIONHI              (0x3 << DMI_DMSTATUS_VERSIONHI_OFFSET)
 630 /*
 631 * 00: There is no Debug Module present.
 632 *
 633 * 01: There is a Debug Module and it conforms to version 0.11 of this
 634 * specification.
 635 *
 636 * 10: There is a Debug Module and it conforms to version 0.13 of this
 637 * specification.
 638 *
 639 * 11: Reserved for future use.
 640  */
 641 #define DMI_DMSTATUS_VERSIONLO_OFFSET       0
 642 #define DMI_DMSTATUS_VERSIONLO_LENGTH       2
 643 #define DMI_DMSTATUS_VERSIONLO              (0x3 << DMI_DMSTATUS_VERSIONLO_OFFSET)
 644 #define DMI_DMCONTROL                       0x10
 645 /*
 646 * Halt request signal for all currently selected harts. When set to 1, the
 647 * hart will halt if it is not currently halted.
 648 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 649 *
 650 * Writes apply to the new value of \Fhartsel and \Fhasel.
 651  */
 652 #define DMI_DMCONTROL_HALTREQ_OFFSET        31
 653 #define DMI_DMCONTROL_HALTREQ_LENGTH        1
 654 #define DMI_DMCONTROL_HALTREQ               (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET)
 655 /*
 656 * Resume request signal for all currently selected harts. When set to 1,
 657 * the hart will resume if it is currently halted.
 658 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 659 *
 660 * Writes apply to the new value of \Fhartsel and \Fhasel.
 661  */
 662 #define DMI_DMCONTROL_RESUMEREQ_OFFSET      30
 663 #define DMI_DMCONTROL_RESUMEREQ_LENGTH      1
 664 #define DMI_DMCONTROL_RESUMEREQ             (0x1 << DMI_DMCONTROL_RESUMEREQ_OFFSET)
 665 /*
 666 * This optional bit controls reset to all the currently selected harts.
 667 * To perform a reset the debugger writes 1, and then writes 0 to
 668 * deassert the reset signal.
 669 *
 670 * If this feature is not implemented, the bit always stays 0, so
 671 * after writing 1 the debugger can read the register back to see if
 672 * the feature is supported.
 673 *
 674 * Writes apply to the new value of \Fhartsel and \Fhasel.
 675  */
 676 #define DMI_DMCONTROL_HARTRESET_OFFSET      29
 677 #define DMI_DMCONTROL_HARTRESET_LENGTH      1
 678 #define DMI_DMCONTROL_HARTRESET             (0x1 << DMI_DMCONTROL_HARTRESET_OFFSET)
 679 /*
 680 * Selects the  definition of currently selected harts.
 681 *
 682 * 0: There is a single currently selected hart, that selected by \Fhartsel.
 683 *
 684 * 1: There may be multiple currently selected harts -- that selected by \Fhartsel,
 685 * plus those selected by the hart array mask register.
 686 *
 687 * An implementation which does not implement the hart array mask register
 688 * should tie this field to 0. A debugger which wishes to use the hart array
 689 * mask register feature should set this bit and read back to see if the functionality
 690 * is supported.
 691  */
 692 #define DMI_DMCONTROL_HASEL_OFFSET          26
 693 #define DMI_DMCONTROL_HASEL_LENGTH          1
 694 #define DMI_DMCONTROL_HASEL                 (0x1 << DMI_DMCONTROL_HASEL_OFFSET)
 695 /*
 696 * The DM-specific index of the hart to select. This hart is always part of the
 697 * currently selected harts.
 698  */
 699 #define DMI_DMCONTROL_HARTSEL_OFFSET        16
 700 #define DMI_DMCONTROL_HARTSEL_LENGTH        10
 701 #define DMI_DMCONTROL_HARTSEL               (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET)
 702 /*
 703 * This bit controls the reset signal from the DM to the rest of the
 704 * system. To perform a reset the debugger writes 1, and then writes 0
 705 * to deassert the reset.
 706  */
 707 #define DMI_DMCONTROL_NDMRESET_OFFSET       1
 708 #define DMI_DMCONTROL_NDMRESET_LENGTH       1
 709 #define DMI_DMCONTROL_NDMRESET              (0x1 << DMI_DMCONTROL_NDMRESET_OFFSET)
 710 /*
 711 * This bit serves as a reset signal for the Debug Module itself.
 712 *
 713 * 0: The module's state, including authentication mechanism,
 714 * takes its reset values (the \Fdmactive bit is the only bit which can
 715 * be written to something other than its reset value).
 716 *
 717 * 1: The module functions normally.
 718 *
 719 * No other mechanism should exist that may result in resetting the
 720 * Debug Module after power up, including the platform's system reset
 721 * or Debug Transport reset signals.
 722 *
 723 * A debugger should pulse this bit low to ensure that the Debug
 724 * Module is fully reset and ready to use.
 725 *
 726 * Implementations may use this bit to aid debugging, for example by
 727 * preventing the Debug Module from being power gated while debugging
 728 * is active.
 729  */
 730 #define DMI_DMCONTROL_DMACTIVE_OFFSET       0
 731 #define DMI_DMCONTROL_DMACTIVE_LENGTH       1
 732 #define DMI_DMCONTROL_DMACTIVE              (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET)
 733 #define DMI_HARTINFO                        0x12
 734 /*
 735 * Number of {\tt dscratch} registers available for the debugger
 736 * to use during program buffer execution, starting from \Rdscratchzero.
 737 * The debugger can make no assumptions about the contents of these
 738 * registers between commands.
 739  */
 740 #define DMI_HARTINFO_NSCRATCH_OFFSET        20
 741 #define DMI_HARTINFO_NSCRATCH_LENGTH        4
 742 #define DMI_HARTINFO_NSCRATCH               (0xf << DMI_HARTINFO_NSCRATCH_OFFSET)
 743 /*
 744 * 0: The {\tt data} registers are shadowed in the hart by CSR
 745 * registers. Each CSR register is XLEN bits in size, and corresponds
 746 * to a single argument, per Table~\ref{tab:datareg}.
 747 *
 748 * 1: The {\tt data} registers are shadowed in the hart's memory map.
 749 * Each register takes up 4 bytes in the memory map.
 750  */
 751 #define DMI_HARTINFO_DATAACCESS_OFFSET      16
 752 #define DMI_HARTINFO_DATAACCESS_LENGTH      1
 753 #define DMI_HARTINFO_DATAACCESS             (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET)
 754 /*
 755 * If \Fdataaccess is 0: Number of CSR registers dedicated to
 756 * shadowing the {\tt data} registers.
 757 *
 758 * If \Fdataaccess is 1: Number of 32-bit words in the memory map
 759 * dedicated to shadowing the {\tt data} registers.
 760  */
 761 #define DMI_HARTINFO_DATASIZE_OFFSET        12
 762 #define DMI_HARTINFO_DATASIZE_LENGTH        4
 763 #define DMI_HARTINFO_DATASIZE               (0xf << DMI_HARTINFO_DATASIZE_OFFSET)
 764 /*
 765 * If \Fdataaccess is 0: The number of the first CSR dedicated to
 766 * shadowing the {\tt data} registers.
 767 *
 768 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
 769 * registers are shadowed.
 770  */
 771 #define DMI_HARTINFO_DATAADDR_OFFSET        0
 772 #define DMI_HARTINFO_DATAADDR_LENGTH        12
 773 #define DMI_HARTINFO_DATAADDR               (0xfff << DMI_HARTINFO_DATAADDR_OFFSET)
 774 #define DMI_HALTSUM                         0x13
 775 #define DMI_HALTSUM_HALT1023_992_OFFSET     31
 776 #define DMI_HALTSUM_HALT1023_992_LENGTH     1
 777 #define DMI_HALTSUM_HALT1023_992            (0x1 << DMI_HALTSUM_HALT1023_992_OFFSET)
 778 #define DMI_HALTSUM_HALT991_960_OFFSET      30
 779 #define DMI_HALTSUM_HALT991_960_LENGTH      1
 780 #define DMI_HALTSUM_HALT991_960             (0x1 << DMI_HALTSUM_HALT991_960_OFFSET)
 781 #define DMI_HALTSUM_HALT959_928_OFFSET      29
 782 #define DMI_HALTSUM_HALT959_928_LENGTH      1
 783 #define DMI_HALTSUM_HALT959_928             (0x1 << DMI_HALTSUM_HALT959_928_OFFSET)
 784 #define DMI_HALTSUM_HALT927_896_OFFSET      28
 785 #define DMI_HALTSUM_HALT927_896_LENGTH      1
 786 #define DMI_HALTSUM_HALT927_896             (0x1 << DMI_HALTSUM_HALT927_896_OFFSET)
 787 #define DMI_HALTSUM_HALT895_864_OFFSET      27
 788 #define DMI_HALTSUM_HALT895_864_LENGTH      1
 789 #define DMI_HALTSUM_HALT895_864             (0x1 << DMI_HALTSUM_HALT895_864_OFFSET)
 790 #define DMI_HALTSUM_HALT863_832_OFFSET      26
 791 #define DMI_HALTSUM_HALT863_832_LENGTH      1
 792 #define DMI_HALTSUM_HALT863_832             (0x1 << DMI_HALTSUM_HALT863_832_OFFSET)
 793 #define DMI_HALTSUM_HALT831_800_OFFSET      25
 794 #define DMI_HALTSUM_HALT831_800_LENGTH      1
 795 #define DMI_HALTSUM_HALT831_800             (0x1 << DMI_HALTSUM_HALT831_800_OFFSET)
 796 #define DMI_HALTSUM_HALT799_768_OFFSET      24
 797 #define DMI_HALTSUM_HALT799_768_LENGTH      1
 798 #define DMI_HALTSUM_HALT799_768             (0x1 << DMI_HALTSUM_HALT799_768_OFFSET)
 799 #define DMI_HALTSUM_HALT767_736_OFFSET      23
 800 #define DMI_HALTSUM_HALT767_736_LENGTH      1
 801 #define DMI_HALTSUM_HALT767_736             (0x1 << DMI_HALTSUM_HALT767_736_OFFSET)
 802 #define DMI_HALTSUM_HALT735_704_OFFSET      22
 803 #define DMI_HALTSUM_HALT735_704_LENGTH      1
 804 #define DMI_HALTSUM_HALT735_704             (0x1 << DMI_HALTSUM_HALT735_704_OFFSET)
 805 #define DMI_HALTSUM_HALT703_672_OFFSET      21
 806 #define DMI_HALTSUM_HALT703_672_LENGTH      1
 807 #define DMI_HALTSUM_HALT703_672             (0x1 << DMI_HALTSUM_HALT703_672_OFFSET)
 808 #define DMI_HALTSUM_HALT671_640_OFFSET      20
 809 #define DMI_HALTSUM_HALT671_640_LENGTH      1
 810 #define DMI_HALTSUM_HALT671_640             (0x1 << DMI_HALTSUM_HALT671_640_OFFSET)
 811 #define DMI_HALTSUM_HALT639_608_OFFSET      19
 812 #define DMI_HALTSUM_HALT639_608_LENGTH      1
 813 #define DMI_HALTSUM_HALT639_608             (0x1 << DMI_HALTSUM_HALT639_608_OFFSET)
 814 #define DMI_HALTSUM_HALT607_576_OFFSET      18
 815 #define DMI_HALTSUM_HALT607_576_LENGTH      1
 816 #define DMI_HALTSUM_HALT607_576             (0x1 << DMI_HALTSUM_HALT607_576_OFFSET)
 817 #define DMI_HALTSUM_HALT575_544_OFFSET      17
 818 #define DMI_HALTSUM_HALT575_544_LENGTH      1
 819 #define DMI_HALTSUM_HALT575_544             (0x1 << DMI_HALTSUM_HALT575_544_OFFSET)
 820 #define DMI_HALTSUM_HALT543_512_OFFSET      16
 821 #define DMI_HALTSUM_HALT543_512_LENGTH      1
 822 #define DMI_HALTSUM_HALT543_512             (0x1 << DMI_HALTSUM_HALT543_512_OFFSET)
 823 #define DMI_HALTSUM_HALT511_480_OFFSET      15
 824 #define DMI_HALTSUM_HALT511_480_LENGTH      1
 825 #define DMI_HALTSUM_HALT511_480             (0x1 << DMI_HALTSUM_HALT511_480_OFFSET)
 826 #define DMI_HALTSUM_HALT479_448_OFFSET      14
 827 #define DMI_HALTSUM_HALT479_448_LENGTH      1
 828 #define DMI_HALTSUM_HALT479_448             (0x1 << DMI_HALTSUM_HALT479_448_OFFSET)
 829 #define DMI_HALTSUM_HALT447_416_OFFSET      13
 830 #define DMI_HALTSUM_HALT447_416_LENGTH      1
 831 #define DMI_HALTSUM_HALT447_416             (0x1 << DMI_HALTSUM_HALT447_416_OFFSET)
 832 #define DMI_HALTSUM_HALT415_384_OFFSET      12
 833 #define DMI_HALTSUM_HALT415_384_LENGTH      1
 834 #define DMI_HALTSUM_HALT415_384             (0x1 << DMI_HALTSUM_HALT415_384_OFFSET)
 835 #define DMI_HALTSUM_HALT383_352_OFFSET      11
 836 #define DMI_HALTSUM_HALT383_352_LENGTH      1
 837 #define DMI_HALTSUM_HALT383_352             (0x1 << DMI_HALTSUM_HALT383_352_OFFSET)
 838 #define DMI_HALTSUM_HALT351_320_OFFSET      10
 839 #define DMI_HALTSUM_HALT351_320_LENGTH      1
 840 #define DMI_HALTSUM_HALT351_320             (0x1 << DMI_HALTSUM_HALT351_320_OFFSET)
 841 #define DMI_HALTSUM_HALT319_288_OFFSET      9
 842 #define DMI_HALTSUM_HALT319_288_LENGTH      1
 843 #define DMI_HALTSUM_HALT319_288             (0x1 << DMI_HALTSUM_HALT319_288_OFFSET)
 844 #define DMI_HALTSUM_HALT287_256_OFFSET      8
 845 #define DMI_HALTSUM_HALT287_256_LENGTH      1
 846 #define DMI_HALTSUM_HALT287_256             (0x1 << DMI_HALTSUM_HALT287_256_OFFSET)
 847 #define DMI_HALTSUM_HALT255_224_OFFSET      7
 848 #define DMI_HALTSUM_HALT255_224_LENGTH      1
 849 #define DMI_HALTSUM_HALT255_224             (0x1 << DMI_HALTSUM_HALT255_224_OFFSET)
 850 #define DMI_HALTSUM_HALT223_192_OFFSET      6
 851 #define DMI_HALTSUM_HALT223_192_LENGTH      1
 852 #define DMI_HALTSUM_HALT223_192             (0x1 << DMI_HALTSUM_HALT223_192_OFFSET)
 853 #define DMI_HALTSUM_HALT191_160_OFFSET      5
 854 #define DMI_HALTSUM_HALT191_160_LENGTH      1
 855 #define DMI_HALTSUM_HALT191_160             (0x1 << DMI_HALTSUM_HALT191_160_OFFSET)
 856 #define DMI_HALTSUM_HALT159_128_OFFSET      4
 857 #define DMI_HALTSUM_HALT159_128_LENGTH      1
 858 #define DMI_HALTSUM_HALT159_128             (0x1 << DMI_HALTSUM_HALT159_128_OFFSET)
 859 #define DMI_HALTSUM_HALT127_96_OFFSET       3
 860 #define DMI_HALTSUM_HALT127_96_LENGTH       1
 861 #define DMI_HALTSUM_HALT127_96              (0x1 << DMI_HALTSUM_HALT127_96_OFFSET)
 862 #define DMI_HALTSUM_HALT95_64_OFFSET        2
 863 #define DMI_HALTSUM_HALT95_64_LENGTH        1
 864 #define DMI_HALTSUM_HALT95_64               (0x1 << DMI_HALTSUM_HALT95_64_OFFSET)
 865 #define DMI_HALTSUM_HALT63_32_OFFSET        1
 866 #define DMI_HALTSUM_HALT63_32_LENGTH        1
 867 #define DMI_HALTSUM_HALT63_32               (0x1 << DMI_HALTSUM_HALT63_32_OFFSET)
 868 #define DMI_HALTSUM_HALT31_0_OFFSET         0
 869 #define DMI_HALTSUM_HALT31_0_LENGTH         1
 870 #define DMI_HALTSUM_HALT31_0                (0x1 << DMI_HALTSUM_HALT31_0_OFFSET)
 871 #define DMI_HAWINDOWSEL                     0x14
 872 #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET  0
 873 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH  5
 874 #define DMI_HAWINDOWSEL_HAWINDOWSEL         (0x1f << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
 875 #define DMI_HAWINDOW                        0x15
 876 #define DMI_HAWINDOW_MASKDATA_OFFSET        0
 877 #define DMI_HAWINDOW_MASKDATA_LENGTH        32
 878 #define DMI_HAWINDOW_MASKDATA               (0xffffffff << DMI_HAWINDOW_MASKDATA_OFFSET)
 879 #define DMI_ABSTRACTCS                      0x16
 880 /*
 881 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
 882 *
 883 * TODO: Explain what can be done with each size of the buffer, to suggest
 884 * why you would want more or less words.
 885  */
 886 #define DMI_ABSTRACTCS_PROGSIZE_OFFSET      24
 887 #define DMI_ABSTRACTCS_PROGSIZE_LENGTH      5
 888 #define DMI_ABSTRACTCS_PROGSIZE             (0x1f << DMI_ABSTRACTCS_PROGSIZE_OFFSET)
 889 /*
 890 * 1: An abstract command is currently being executed.
 891 *
 892 * This bit is set as soon as \Rcommand is written, and is
 893 * not cleared until that command has completed.
 894  */
 895 #define DMI_ABSTRACTCS_BUSY_OFFSET          12
 896 #define DMI_ABSTRACTCS_BUSY_LENGTH          1
 897 #define DMI_ABSTRACTCS_BUSY                 (0x1 << DMI_ABSTRACTCS_BUSY_OFFSET)
 898 /*
 899 * Gets set if an abstract command fails. The bits in this field remain set until
 900 * they are cleared by writing 1 to them. No abstract command is
 901 * started until the value is reset to 0.
 902 *
 903 * 0 (none): No error.
 904 *
 905 * 1 (busy): An abstract command was executing while \Rcommand or one
 906 * of the {\tt data} registers was accessed.
 907 *
 908 * 2 (not supported): The requested command is not supported. A
 909 * command that is not supported while the hart is running may be
 910 * supported when it is halted.
 911 *
 912 * 3 (exception): An exception occurred while executing the command
 913 * (eg. while executing the Program Buffer).
 914 *
 915 * 4 (halt/resume): An abstract command couldn't execute because the
 916 * hart wasn't in the expected state (running/halted).
 917 *
 918 * 7 (other): The command failed for another reason.
 919  */
 920 #define DMI_ABSTRACTCS_CMDERR_OFFSET        8
 921 #define DMI_ABSTRACTCS_CMDERR_LENGTH        3
 922 #define DMI_ABSTRACTCS_CMDERR               (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET)
 923 /*
 924 * Number of {\tt data} registers that are implemented as part of the
 925 * abstract command interface. Valid sizes are 0 - 8.
 926  */
 927 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET     0
 928 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH     5
 929 #define DMI_ABSTRACTCS_DATACOUNT            (0x1f << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
 930 #define DMI_COMMAND                         0x17
 931 /*
 932 * The type determines the overall functionality of this
 933 * abstract command.
 934  */
 935 #define DMI_COMMAND_CMDTYPE_OFFSET          24
 936 #define DMI_COMMAND_CMDTYPE_LENGTH          8
 937 #define DMI_COMMAND_CMDTYPE                 (0xff << DMI_COMMAND_CMDTYPE_OFFSET)
 938 /*
 939 * This field is interpreted in a command-specific manner,
 940 * described for each abstract command.
 941  */
 942 #define DMI_COMMAND_CONTROL_OFFSET          0
 943 #define DMI_COMMAND_CONTROL_LENGTH          24
 944 #define DMI_COMMAND_CONTROL                 (0xffffff << DMI_COMMAND_CONTROL_OFFSET)
 945 #define DMI_ABSTRACTAUTO                    0x18
 946 /*
 947 * When a bit in this field is 1, read or write accesses the corresponding {\tt progbuf} word
 948 * cause the command in \Rcommand to be executed again.
 949  */
 950 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
 951 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
 952 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF    (0xffff << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
 953 /*
 954 * When a bit in this field is 1, read or write accesses the corresponding {\tt data} word
 955 * cause the command in \Rcommand to be executed again.
 956  */
 957 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
 958 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
 959 #define DMI_ABSTRACTAUTO_AUTOEXECDATA       (0xfff << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
 960 #define DMI_CFGSTRADDR0                     0x19
 961 #define DMI_CFGSTRADDR0_ADDR_OFFSET         0
 962 #define DMI_CFGSTRADDR0_ADDR_LENGTH         32
 963 #define DMI_CFGSTRADDR0_ADDR                (0xffffffff << DMI_CFGSTRADDR0_ADDR_OFFSET)
 964 #define DMI_CFGSTRADDR1                     0x1a
 965 #define DMI_CFGSTRADDR2                     0x1b
 966 #define DMI_CFGSTRADDR3                     0x1c
 967 #define DMI_DATA0                           0x04
 968 #define DMI_DATA0_DATA_OFFSET               0
 969 #define DMI_DATA0_DATA_LENGTH               32
 970 #define DMI_DATA0_DATA                      (0xffffffff << DMI_DATA0_DATA_OFFSET)
 971 #define DMI_DATA11                          0x0f
 972 #define DMI_PROGBUF0                        0x20
 973 #define DMI_PROGBUF0_DATA_OFFSET            0
 974 #define DMI_PROGBUF0_DATA_LENGTH            32
 975 #define DMI_PROGBUF0_DATA                   (0xffffffff << DMI_PROGBUF0_DATA_OFFSET)
 976 #define DMI_PROGBUF15                       0x2f
 977 #define DMI_AUTHDATA                        0x30
 978 #define DMI_AUTHDATA_DATA_OFFSET            0
 979 #define DMI_AUTHDATA_DATA_LENGTH            32
 980 #define DMI_AUTHDATA_DATA                   (0xffffffff << DMI_AUTHDATA_DATA_OFFSET)
 981 #define DMI_SERCS                           0x34
 982 /*
 983 * Number of supported serial ports.
 984  */
 985 #define DMI_SERCS_SERIALCOUNT_OFFSET        28
 986 #define DMI_SERCS_SERIALCOUNT_LENGTH        4
 987 #define DMI_SERCS_SERIALCOUNT               (0xf << DMI_SERCS_SERIALCOUNT_OFFSET)
 988 /*
 989 * Select which serial port is accessed by \Rserrx and \Rsertx.
 990  */
 991 #define DMI_SERCS_SERIAL_OFFSET             24
 992 #define DMI_SERCS_SERIAL_LENGTH             3
 993 #define DMI_SERCS_SERIAL                    (0x7 << DMI_SERCS_SERIAL_OFFSET)
 994 #define DMI_SERCS_ERROR7_OFFSET             23
 995 #define DMI_SERCS_ERROR7_LENGTH             1
 996 #define DMI_SERCS_ERROR7                    (0x1 << DMI_SERCS_ERROR7_OFFSET)
 997 #define DMI_SERCS_VALID7_OFFSET             22
 998 #define DMI_SERCS_VALID7_LENGTH             1
 999 #define DMI_SERCS_VALID7                    (0x1 << DMI_SERCS_VALID7_OFFSET)
1000 #define DMI_SERCS_FULL7_OFFSET              21
1001 #define DMI_SERCS_FULL7_LENGTH              1
1002 #define DMI_SERCS_FULL7                     (0x1 << DMI_SERCS_FULL7_OFFSET)
1003 #define DMI_SERCS_ERROR6_OFFSET             20
1004 #define DMI_SERCS_ERROR6_LENGTH             1
1005 #define DMI_SERCS_ERROR6                    (0x1 << DMI_SERCS_ERROR6_OFFSET)
1006 #define DMI_SERCS_VALID6_OFFSET             19
1007 #define DMI_SERCS_VALID6_LENGTH             1
1008 #define DMI_SERCS_VALID6                    (0x1 << DMI_SERCS_VALID6_OFFSET)
1009 #define DMI_SERCS_FULL6_OFFSET              18
1010 #define DMI_SERCS_FULL6_LENGTH              1
1011 #define DMI_SERCS_FULL6                     (0x1 << DMI_SERCS_FULL6_OFFSET)
1012 #define DMI_SERCS_ERROR5_OFFSET             17
1013 #define DMI_SERCS_ERROR5_LENGTH             1
1014 #define DMI_SERCS_ERROR5                    (0x1 << DMI_SERCS_ERROR5_OFFSET)
1015 #define DMI_SERCS_VALID5_OFFSET             16
1016 #define DMI_SERCS_VALID5_LENGTH             1
1017 #define DMI_SERCS_VALID5                    (0x1 << DMI_SERCS_VALID5_OFFSET)
1018 #define DMI_SERCS_FULL5_OFFSET              15
1019 #define DMI_SERCS_FULL5_LENGTH              1
1020 #define DMI_SERCS_FULL5                     (0x1 << DMI_SERCS_FULL5_OFFSET)
1021 #define DMI_SERCS_ERROR4_OFFSET             14
1022 #define DMI_SERCS_ERROR4_LENGTH             1
1023 #define DMI_SERCS_ERROR4                    (0x1 << DMI_SERCS_ERROR4_OFFSET)
1024 #define DMI_SERCS_VALID4_OFFSET             13
1025 #define DMI_SERCS_VALID4_LENGTH             1
1026 #define DMI_SERCS_VALID4                    (0x1 << DMI_SERCS_VALID4_OFFSET)
1027 #define DMI_SERCS_FULL4_OFFSET              12
1028 #define DMI_SERCS_FULL4_LENGTH              1
1029 #define DMI_SERCS_FULL4                     (0x1 << DMI_SERCS_FULL4_OFFSET)
1030 #define DMI_SERCS_ERROR3_OFFSET             11
1031 #define DMI_SERCS_ERROR3_LENGTH             1
1032 #define DMI_SERCS_ERROR3                    (0x1 << DMI_SERCS_ERROR3_OFFSET)
1033 #define DMI_SERCS_VALID3_OFFSET             10
1034 #define DMI_SERCS_VALID3_LENGTH             1
1035 #define DMI_SERCS_VALID3                    (0x1 << DMI_SERCS_VALID3_OFFSET)
1036 #define DMI_SERCS_FULL3_OFFSET              9
1037 #define DMI_SERCS_FULL3_LENGTH              1
1038 #define DMI_SERCS_FULL3                     (0x1 << DMI_SERCS_FULL3_OFFSET)
1039 #define DMI_SERCS_ERROR2_OFFSET             8
1040 #define DMI_SERCS_ERROR2_LENGTH             1
1041 #define DMI_SERCS_ERROR2                    (0x1 << DMI_SERCS_ERROR2_OFFSET)
1042 #define DMI_SERCS_VALID2_OFFSET             7
1043 #define DMI_SERCS_VALID2_LENGTH             1
1044 #define DMI_SERCS_VALID2                    (0x1 << DMI_SERCS_VALID2_OFFSET)
1045 #define DMI_SERCS_FULL2_OFFSET              6
1046 #define DMI_SERCS_FULL2_LENGTH              1
1047 #define DMI_SERCS_FULL2                     (0x1 << DMI_SERCS_FULL2_OFFSET)
1048 #define DMI_SERCS_ERROR1_OFFSET             5
1049 #define DMI_SERCS_ERROR1_LENGTH             1
1050 #define DMI_SERCS_ERROR1                    (0x1 << DMI_SERCS_ERROR1_OFFSET)
1051 #define DMI_SERCS_VALID1_OFFSET             4
1052 #define DMI_SERCS_VALID1_LENGTH             1
1053 #define DMI_SERCS_VALID1                    (0x1 << DMI_SERCS_VALID1_OFFSET)
1054 #define DMI_SERCS_FULL1_OFFSET              3
1055 #define DMI_SERCS_FULL1_LENGTH              1
1056 #define DMI_SERCS_FULL1                     (0x1 << DMI_SERCS_FULL1_OFFSET)
1057 /*
1058 * 1 when the debugger-to-core queue for serial port 0 has
1059 * over or underflowed. This bit will remain set until it is reset by
1060 * writing 1 to this bit.
1061  */
1062 #define DMI_SERCS_ERROR0_OFFSET             2
1063 #define DMI_SERCS_ERROR0_LENGTH             1
1064 #define DMI_SERCS_ERROR0                    (0x1 << DMI_SERCS_ERROR0_OFFSET)
1065 /*
1066 * 1 when the core-to-debugger queue for serial port 0 is not empty.
1067  */
1068 #define DMI_SERCS_VALID0_OFFSET             1
1069 #define DMI_SERCS_VALID0_LENGTH             1
1070 #define DMI_SERCS_VALID0                    (0x1 << DMI_SERCS_VALID0_OFFSET)
1071 /*
1072 * 1 when the debugger-to-core queue for serial port 0 is full.
1073  */
1074 #define DMI_SERCS_FULL0_OFFSET              0
1075 #define DMI_SERCS_FULL0_LENGTH              1
1076 #define DMI_SERCS_FULL0                     (0x1 << DMI_SERCS_FULL0_OFFSET)
1077 #define DMI_SERTX                           0x35
1078 #define DMI_SERTX_DATA_OFFSET               0
1079 #define DMI_SERTX_DATA_LENGTH               32
1080 #define DMI_SERTX_DATA                      (0xffffffff << DMI_SERTX_DATA_OFFSET)
1081 #define DMI_SERRX                           0x36
1082 #define DMI_SERRX_DATA_OFFSET               0
1083 #define DMI_SERRX_DATA_LENGTH               32
1084 #define DMI_SERRX_DATA                      (0xffffffff << DMI_SERRX_DATA_OFFSET)
1085 #define DMI_SBCS                            0x38
1086 /*
1087 * When a 1 is written here, triggers a read at the address in {\tt
1088 * sbaddress} using the access size set by \Fsbaccess.
1089  */
1090 #define DMI_SBCS_SBSINGLEREAD_OFFSET        20
1091 #define DMI_SBCS_SBSINGLEREAD_LENGTH        1
1092 #define DMI_SBCS_SBSINGLEREAD               (0x1 << DMI_SBCS_SBSINGLEREAD_OFFSET)
1093 /*
1094 * Select the access size to use for system bus accesses triggered by
1095 * writes to the {\tt sbaddress} registers or \Rsbdatazero.
1096 *
1097 * 0: 8-bit
1098 *
1099 * 1: 16-bit
1100 *
1101 * 2: 32-bit
1102 *
1103 * 3: 64-bit
1104 *
1105 * 4: 128-bit
1106 *
1107 * If an unsupported system bus access size is written here,
1108 * the DM may not perform the access, or may perform the access
1109 * with any access size.
1110  */
1111 #define DMI_SBCS_SBACCESS_OFFSET            17
1112 #define DMI_SBCS_SBACCESS_LENGTH            3
1113 #define DMI_SBCS_SBACCESS                   (0x7 << DMI_SBCS_SBACCESS_OFFSET)
1114 /*
1115 * When 1, the internal address value (used by the system bus master)
1116 * is incremented by the access size (in bytes) selected in \Fsbaccess
1117 * after every system bus access.
1118  */
1119 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET     16
1120 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH     1
1121 #define DMI_SBCS_SBAUTOINCREMENT            (0x1 << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
1122 /*
1123 * When 1, every read from \Rsbdatazero automatically triggers a system
1124 * bus read at the new address.
1125  */
1126 #define DMI_SBCS_SBAUTOREAD_OFFSET          15
1127 #define DMI_SBCS_SBAUTOREAD_LENGTH          1
1128 #define DMI_SBCS_SBAUTOREAD                 (0x1 << DMI_SBCS_SBAUTOREAD_OFFSET)
1129 /*
1130 * When the debug module's system bus
1131 * master causes a bus error, this field gets set. The bits in this
1132 * field remain set until they are cleared by writing 1 to them.
1133 * While this field is non-zero, no more system bus accesses can be
1134 * initiated by the debug module.
1135 *
1136 * 0: There was no bus error.
1137 *
1138 * 1: There was a timeout.
1139 *
1140 * 2: A bad address was accessed.
1141 *
1142 * 3: There was some other error (eg. alignment).
1143 *
1144 * 4: The system bus master was busy when a one of the
1145 * {\tt sbaddress} or {\tt sbdata} registers was written,
1146 * or the {\tt sbdata} register was read when it had
1147 * stale data.
1148  */
1149 #define DMI_SBCS_SBERROR_OFFSET             12
1150 #define DMI_SBCS_SBERROR_LENGTH             3
1151 #define DMI_SBCS_SBERROR                    (0x7 << DMI_SBCS_SBERROR_OFFSET)
1152 /*
1153 * Width of system bus addresses in bits. (0 indicates there is no bus
1154 * access support.)
1155  */
1156 #define DMI_SBCS_SBASIZE_OFFSET             5
1157 #define DMI_SBCS_SBASIZE_LENGTH             7
1158 #define DMI_SBCS_SBASIZE                    (0x7f << DMI_SBCS_SBASIZE_OFFSET)
1159 /*
1160 * 1 when 128-bit system bus accesses are supported.
1161  */
1162 #define DMI_SBCS_SBACCESS128_OFFSET         4
1163 #define DMI_SBCS_SBACCESS128_LENGTH         1
1164 #define DMI_SBCS_SBACCESS128                (0x1 << DMI_SBCS_SBACCESS128_OFFSET)
1165 /*
1166 * 1 when 64-bit system bus accesses are supported.
1167  */
1168 #define DMI_SBCS_SBACCESS64_OFFSET          3
1169 #define DMI_SBCS_SBACCESS64_LENGTH          1
1170 #define DMI_SBCS_SBACCESS64                 (0x1 << DMI_SBCS_SBACCESS64_OFFSET)
1171 /*
1172 * 1 when 32-bit system bus accesses are supported.
1173  */
1174 #define DMI_SBCS_SBACCESS32_OFFSET          2
1175 #define DMI_SBCS_SBACCESS32_LENGTH          1
1176 #define DMI_SBCS_SBACCESS32                 (0x1 << DMI_SBCS_SBACCESS32_OFFSET)
1177 /*
1178 * 1 when 16-bit system bus accesses are supported.
1179  */
1180 #define DMI_SBCS_SBACCESS16_OFFSET          1
1181 #define DMI_SBCS_SBACCESS16_LENGTH          1
1182 #define DMI_SBCS_SBACCESS16                 (0x1 << DMI_SBCS_SBACCESS16_OFFSET)
1183 /*
1184 * 1 when 8-bit system bus accesses are supported.
1185  */
1186 #define DMI_SBCS_SBACCESS8_OFFSET           0
1187 #define DMI_SBCS_SBACCESS8_LENGTH           1
1188 #define DMI_SBCS_SBACCESS8                  (0x1 << DMI_SBCS_SBACCESS8_OFFSET)
1189 #define DMI_SBADDRESS0                      0x39
1190 /*
1191 * Accesses bits 31:0 of the internal address.
1192  */
1193 #define DMI_SBADDRESS0_ADDRESS_OFFSET       0
1194 #define DMI_SBADDRESS0_ADDRESS_LENGTH       32
1195 #define DMI_SBADDRESS0_ADDRESS              (0xffffffff << DMI_SBADDRESS0_ADDRESS_OFFSET)
1196 #define DMI_SBADDRESS1                      0x3a
1197 /*
1198 * Accesses bits 63:32 of the internal address (if the system address
1199 * bus is that wide).
1200  */
1201 #define DMI_SBADDRESS1_ADDRESS_OFFSET       0
1202 #define DMI_SBADDRESS1_ADDRESS_LENGTH       32
1203 #define DMI_SBADDRESS1_ADDRESS              (0xffffffff << DMI_SBADDRESS1_ADDRESS_OFFSET)
1204 #define DMI_SBADDRESS2                      0x3b
1205 /*
1206 * Accesses bits 95:64 of the internal address (if the system address
1207 * bus is that wide).
1208  */
1209 #define DMI_SBADDRESS2_ADDRESS_OFFSET       0
1210 #define DMI_SBADDRESS2_ADDRESS_LENGTH       32
1211 #define DMI_SBADDRESS2_ADDRESS              (0xffffffff << DMI_SBADDRESS2_ADDRESS_OFFSET)
1212 #define DMI_SBDATA0                         0x3c
1213 /*
1214 * Accesses bits 31:0 of the internal data.
1215  */
1216 #define DMI_SBDATA0_DATA_OFFSET             0
1217 #define DMI_SBDATA0_DATA_LENGTH             32
1218 #define DMI_SBDATA0_DATA                    (0xffffffff << DMI_SBDATA0_DATA_OFFSET)
1219 #define DMI_SBDATA1                         0x3d
1220 /*
1221 * Accesses bits 63:32 of the internal data (if the system bus is
1222 * that wide).
1223  */
1224 #define DMI_SBDATA1_DATA_OFFSET             0
1225 #define DMI_SBDATA1_DATA_LENGTH             32
1226 #define DMI_SBDATA1_DATA                    (0xffffffff << DMI_SBDATA1_DATA_OFFSET)
1227 #define DMI_SBDATA2                         0x3e
1228 /*
1229 * Accesses bits 95:64 of the internal data (if the system bus is
1230 * that wide).
1231  */
1232 #define DMI_SBDATA2_DATA_OFFSET             0
1233 #define DMI_SBDATA2_DATA_LENGTH             32
1234 #define DMI_SBDATA2_DATA                    (0xffffffff << DMI_SBDATA2_DATA_OFFSET)
1235 #define DMI_SBDATA3                         0x3f
1236 /*
1237 * Accesses bits 127:96 of the internal data (if the system bus is
1238 * that wide).
1239  */
1240 #define DMI_SBDATA3_DATA_OFFSET             0
1241 #define DMI_SBDATA3_DATA_LENGTH             32
1242 #define DMI_SBDATA3_DATA                    (0xffffffff << DMI_SBDATA3_DATA_OFFSET)
1243 #define TRACE                               0x728
1244 /*
1245 * 1 if the trace buffer has wrapped since the last time \Fdiscard was
1246 * written. 0 otherwise.
1247  */
1248 #define TRACE_WRAPPED_OFFSET                24
1249 #define TRACE_WRAPPED_LENGTH                1
1250 #define TRACE_WRAPPED                       (0x1 << TRACE_WRAPPED_OFFSET)
1251 /*
1252 * Emit Timestamp trace sequences.
1253  */
1254 #define TRACE_EMITTIMESTAMP_OFFSET          23
1255 #define TRACE_EMITTIMESTAMP_LENGTH          1
1256 #define TRACE_EMITTIMESTAMP                 (0x1 << TRACE_EMITTIMESTAMP_OFFSET)
1257 /*
1258 * Emit Store Data trace sequences.
1259  */
1260 #define TRACE_EMITSTOREDATA_OFFSET          22
1261 #define TRACE_EMITSTOREDATA_LENGTH          1
1262 #define TRACE_EMITSTOREDATA                 (0x1 << TRACE_EMITSTOREDATA_OFFSET)
1263 /*
1264 * Emit Load Data trace sequences.
1265  */
1266 #define TRACE_EMITLOADDATA_OFFSET           21
1267 #define TRACE_EMITLOADDATA_LENGTH           1
1268 #define TRACE_EMITLOADDATA                  (0x1 << TRACE_EMITLOADDATA_OFFSET)
1269 /*
1270 * Emit Store Address trace sequences.
1271  */
1272 #define TRACE_EMITSTOREADDR_OFFSET          20
1273 #define TRACE_EMITSTOREADDR_LENGTH          1
1274 #define TRACE_EMITSTOREADDR                 (0x1 << TRACE_EMITSTOREADDR_OFFSET)
1275 /*
1276 * Emit Load Address trace sequences.
1277  */
1278 #define TRACE_EMITLOADADDR_OFFSET           19
1279 #define TRACE_EMITLOADADDR_LENGTH           1
1280 #define TRACE_EMITLOADADDR                  (0x1 << TRACE_EMITLOADADDR_OFFSET)
1281 /*
1282 * Emit Privilege Level trace sequences.
1283  */
1284 #define TRACE_EMITPRIV_OFFSET               18
1285 #define TRACE_EMITPRIV_LENGTH               1
1286 #define TRACE_EMITPRIV                      (0x1 << TRACE_EMITPRIV_OFFSET)
1287 /*
1288 * Emit Branch Taken and Branch Not Taken trace sequences.
1289  */
1290 #define TRACE_EMITBRANCH_OFFSET             17
1291 #define TRACE_EMITBRANCH_LENGTH             1
1292 #define TRACE_EMITBRANCH                    (0x1 << TRACE_EMITBRANCH_OFFSET)
1293 /*
1294 * Emit PC trace sequences.
1295  */
1296 #define TRACE_EMITPC_OFFSET                 16
1297 #define TRACE_EMITPC_LENGTH                 1
1298 #define TRACE_EMITPC                        (0x1 << TRACE_EMITPC_OFFSET)
1299 /*
1300 * Determine what happens when the trace buffer is full.  0 means wrap
1301 * and overwrite. 1 means turn off trace until \Fdiscard is written as 1.
1302 * 2 means cause a trace full exception. 3 is reserved for future use.
1303  */
1304 #define TRACE_FULLACTION_OFFSET             8
1305 #define TRACE_FULLACTION_LENGTH             2
1306 #define TRACE_FULLACTION                    (0x3 << TRACE_FULLACTION_OFFSET)
1307 /*
1308 * 0: Trace to a dedicated on-core RAM (which is not further defined in
1309 * this spec).
1310 *
1311 * 1: Trace to RAM on the system bus.
1312 *
1313 * 2: Send trace data to a dedicated off-chip interface (which is not
1314 * defined in this spec). This does not affect execution speed.
1315 *
1316 * 3: Reserved for future use.
1317 *
1318 * Options 0 and 1 slow down execution (eg. because of system bus
1319 * contention).
1320  */
1321 #define TRACE_DESTINATION_OFFSET            4
1322 #define TRACE_DESTINATION_LENGTH            2
1323 #define TRACE_DESTINATION                   (0x3 << TRACE_DESTINATION_OFFSET)
1324 /*
1325 * When 1, the trace logic may stall processor execution to ensure it
1326 * can emit all the trace sequences required. When 0 individual trace
1327 * sequences may be dropped.
1328  */
1329 #define TRACE_STALL_OFFSET                  2
1330 #define TRACE_STALL_LENGTH                  1
1331 #define TRACE_STALL                         (0x1 << TRACE_STALL_OFFSET)
1332 /*
1333 * Writing 1 to this bit tells the trace logic that any trace
1334 * collected is no longer required. When tracing to RAM, it resets the
1335 * trace write pointer to the start of the memory, as well as
1336 * \Fwrapped.
1337  */
1338 #define TRACE_DISCARD_OFFSET                1
1339 #define TRACE_DISCARD_LENGTH                1
1340 #define TRACE_DISCARD                       (0x1 << TRACE_DISCARD_OFFSET)
1341 #define TRACE_SUPPORTED_OFFSET              0
1342 #define TRACE_SUPPORTED_LENGTH              1
1343 #define TRACE_SUPPORTED                     (0x1 << TRACE_SUPPORTED_OFFSET)
1344 #define TBUFSTART                           0x729
1345 #define TBUFEND                             0x72a
1346 #define TBUFWRITE                           0x72b
1347 #define SHORTNAME                           0x123
1348 /*
1349 * Description of what this field is used for.
1350  */
1351 #define SHORTNAME_FIELD_OFFSET              0
1352 #define SHORTNAME_FIELD_LENGTH              8
1353 #define SHORTNAME_FIELD                     (0xff << SHORTNAME_FIELD_OFFSET)
1354 #define AC_ACCESS_REGISTER                  None
1355 /*
1356 * This is 0 to indicate Access Register Command.
1357  */
1358 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET   24
1359 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH   8
1360 #define AC_ACCESS_REGISTER_CMDTYPE          (0xff << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
1361 /*
1362 * 2: Access the lowest 32 bits of the register.
1363 *
1364 * 3: Access the lowest 64 bits of the register.
1365 *
1366 * 4: Access the lowest 128 bits of the register.
1367 *
1368 * If \Fsize specifies a size larger than the register's actual size,
1369 * then the access must fail. If a register is accessible, then reads of \Fsize
1370 * less than or equal to the register's actual size must be supported.
1371  */
1372 #define AC_ACCESS_REGISTER_SIZE_OFFSET      20
1373 #define AC_ACCESS_REGISTER_SIZE_LENGTH      3
1374 #define AC_ACCESS_REGISTER_SIZE             (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET)
1375 /*
1376 * When 1, execute the program in the Program Buffer exactly once
1377 * after performing the transfer, if any.
1378  */
1379 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET  18
1380 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH  1
1381 #define AC_ACCESS_REGISTER_POSTEXEC         (0x1 << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1382 /*
1383 * 0: Don't do the operation specified by \Fwrite.
1384 *
1385 * 1: Do the operation specified by \Fwrite.
1386  */
1387 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET  17
1388 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH  1
1389 #define AC_ACCESS_REGISTER_TRANSFER         (0x1 << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
1390 /*
1391 * When \Ftransfer is set:
1392 * 0: Copy data from the specified register into {\tt arg0} portion
1393 * of {\tt data}.
1394 *
1395 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1396 * specified register.
1397  */
1398 #define AC_ACCESS_REGISTER_WRITE_OFFSET     16
1399 #define AC_ACCESS_REGISTER_WRITE_LENGTH     1
1400 #define AC_ACCESS_REGISTER_WRITE            (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET)
1401 /*
1402 * Number of the register to access, as described in Table~\ref{tab:regno}.
1403  */
1404 #define AC_ACCESS_REGISTER_REGNO_OFFSET     0
1405 #define AC_ACCESS_REGISTER_REGNO_LENGTH     16
1406 #define AC_ACCESS_REGISTER_REGNO            (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET)
1407 #define AC_QUICK_ACCESS                     None
1408 /*
1409 * This is 1 to indicate Quick Access command.
1410  */
1411 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET      24
1412 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH      8
1413 #define AC_QUICK_ACCESS_CMDTYPE             (0xff << AC_QUICK_ACCESS_CMDTYPE_OFFSET)