riscv/debug_defines.h

   1 #define DTM_IDCODE                          0x01
   2 /*
   3 * Identifies the release version of this part.
   4  */
   5 #define DTM_IDCODE_VERSION_OFFSET           28
   6 #define DTM_IDCODE_VERSION_LENGTH           4
   7 #define DTM_IDCODE_VERSION                  (0xf << DTM_IDCODE_VERSION_OFFSET)
   8 /*
   9 * Identifies the designer's part number of this part.
  10  */
  11 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
  12 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
  13 #define DTM_IDCODE_PARTNUMBER               (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET)
  14 /*
  15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
  16 * bits 6:0 of the designer/manufacturer's Identification Code as
  17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
  18 * count of the number of continuation characters (0x7f) in that same
  19 * Identification Code.
  20  */
  21 #define DTM_IDCODE_MANUFID_OFFSET           1
  22 #define DTM_IDCODE_MANUFID_LENGTH           11
  23 #define DTM_IDCODE_MANUFID                  (0x7ff << DTM_IDCODE_MANUFID_OFFSET)
  24 #define DTM_IDCODE_1_OFFSET                 0
  25 #define DTM_IDCODE_1_LENGTH                 1
  26 #define DTM_IDCODE_1                        (0x1 << DTM_IDCODE_1_OFFSET)
  27 #define DTM_DTMCS                           0x10
  28 /*
  29 * Writing 1 to this bit resets the DMI controller, clearing any
  30 * sticky error state.
  31  */
  32 #define DTM_DTMCS_DMIRESET_OFFSET           16
  33 #define DTM_DTMCS_DMIRESET_LENGTH           1
  34 #define DTM_DTMCS_DMIRESET                  (0x1 << DTM_DTMCS_DMIRESET_OFFSET)
  35 /*
  36 * This is the minimum number of cycles a debugger should spend in
  37 * Run-Test/Idle after every DMI scan to avoid a 'busy'
  38 * return code (\Fdmistat of 3). A debugger must still
  39 * check \Fdmistat when necessary.
  40 *
  41 * 0: It is not necessary to enter Run-Test/Idle at all.
  42 *
  43 * 1: Enter Run-Test/Idle and leave it immediately.
  44 *
  45 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
  46 *
  47 * And so on.
  48  */
  49 #define DTM_DTMCS_IDLE_OFFSET               12
  50 #define DTM_DTMCS_IDLE_LENGTH               3
  51 #define DTM_DTMCS_IDLE                      (0x7 << DTM_DTMCS_IDLE_OFFSET)
  52 /*
  53 * 0: No error.
  54 *
  55 * 1: Reserved. Interpret the same as 2.
  56 *
  57 * 2: An operation failed (resulted in \Fop of 2).
  58 *
  59 * 3: An operation was attempted while a DMI access was still in
  60 * progress (resulted in \Fop of 3).
  61  */
  62 #define DTM_DTMCS_DMISTAT_OFFSET            10
  63 #define DTM_DTMCS_DMISTAT_LENGTH            2
  64 #define DTM_DTMCS_DMISTAT                   (0x3 << DTM_DTMCS_DMISTAT_OFFSET)
  65 /*
  66 * The size of \Faddress in \Rdmi.
  67  */
  68 #define DTM_DTMCS_ABITS_OFFSET              4
  69 #define DTM_DTMCS_ABITS_LENGTH              6
  70 #define DTM_DTMCS_ABITS                     (0x3f << DTM_DTMCS_ABITS_OFFSET)
  71 /*
  72 * 0: Version described in spec version 0.11.
  73 *
  74 * 1: Version described in spec version 0.12 (and later?), which
  75 * reduces the DMI data width to 32 bits.
  76 *
  77 * Other values are reserved for future use.
  78  */
  79 #define DTM_DTMCS_VERSION_OFFSET            0
  80 #define DTM_DTMCS_VERSION_LENGTH            4
  81 #define DTM_DTMCS_VERSION                   (0xf << DTM_DTMCS_VERSION_OFFSET)
  82 #define DTM_DMI                             0x11
  83 /*
  84 * Address used for DMI access. In Update-DR this value is used
  85 * to access the DM over the DMI.
  86  */
  87 #define DTM_DMI_ADDRESS_OFFSET              34
  88 #define DTM_DMI_ADDRESS_LENGTH              abits
  89 #define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
  90 /*
  91 * The data to send to the DM over the DMI during Update-DR, and
  92 * the data returned from the DM as a result of the previous operation.
  93  */
  94 #define DTM_DMI_DATA_OFFSET                 2
  95 #define DTM_DMI_DATA_LENGTH                 32
  96 #define DTM_DMI_DATA                        (0xffffffffL << DTM_DMI_DATA_OFFSET)
  97 /*
  98 * When the debugger writes this field, it has the following meaning:
  99 *
 100 * 0: Ignore \Fdata. (nop)
 101 *
 102 * 1: Read from \Faddress. (read)
 103 *
 104 * 2: Write \Fdata to \Faddress. (write)
 105 *
 106 * 3: Reserved.
 107 *
 108 * When the debugger reads this field, it means the following:
 109 *
 110 * 0: The previous operation completed successfully.
 111 *
 112 * 1: Reserved.
 113 *
 114 * 2: A previous operation failed.  The data scanned into \Rdmi in
 115 * this access will be ignored.  This status is sticky and can be
 116 * cleared by writing \Fdmireset in \Rdtmcs.
 117 *
 118 * This indicates that the DM itself responded with an error, e.g.
 119 * in the System Bus and Serial Port overflow/underflow cases.
 120 *
 121 * 3: An operation was attempted while a DMI request is still in
 122 * progress. The data scanned into \Rdmi in this access will be
 123 * ignored. This status is sticky and can be cleared by writing
 124 * \Fdmireset in \Rdtmcs. If a debugger sees this status, it
 125 * needs to give the target more TCK edges between Update-DR and
 126 * Capture-DR. The simplest way to do that is to add extra transitions
 127 * in Run-Test/Idle.
 128 *
 129 * (The DTM, DM, and/or component may be in different clock domains,
 130 * so synchronization may be required. Some relatively fixed number of
 131 * TCK ticks may be needed for the request to reach the DM, complete,
 132 * and for the response to be synchronized back into the TCK domain.)
 133  */
 134 #define DTM_DMI_OP_OFFSET                   0
 135 #define DTM_DMI_OP_LENGTH                   2
 136 #define DTM_DMI_OP                          (0x3L << DTM_DMI_OP_OFFSET)
 137 #define CSR_DCSR                            0x7b0
 138 /*
 139 * 0: There is no external debug support.
 140 *
 141 * 1: External debug support exists as it is described in this document.
 142 *
 143 * Other values are reserved for future standards.
 144  */
 145 #define CSR_DCSR_XDEBUGVER_OFFSET           30
 146 #define CSR_DCSR_XDEBUGVER_LENGTH           2
 147 #define CSR_DCSR_XDEBUGVER                  (0x3 << CSR_DCSR_XDEBUGVER_OFFSET)
 148 /*
 149 * When 1, {\tt ebreak} instructions in Machine Mode enter Halt Mode.
 150  */
 151 #define CSR_DCSR_EBREAKM_OFFSET             15
 152 #define CSR_DCSR_EBREAKM_LENGTH             1
 153 #define CSR_DCSR_EBREAKM                    (0x1 << CSR_DCSR_EBREAKM_OFFSET)
 154 /*
 155 * When 1, {\tt ebreak} instructions in Hypervisor Mode enter Halt Mode.
 156  */
 157 #define CSR_DCSR_EBREAKH_OFFSET             14
 158 #define CSR_DCSR_EBREAKH_LENGTH             1
 159 #define CSR_DCSR_EBREAKH                    (0x1 << CSR_DCSR_EBREAKH_OFFSET)
 160 /*
 161 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Halt Mode.
 162  */
 163 #define CSR_DCSR_EBREAKS_OFFSET             13
 164 #define CSR_DCSR_EBREAKS_LENGTH             1
 165 #define CSR_DCSR_EBREAKS                    (0x1 << CSR_DCSR_EBREAKS_OFFSET)
 166 /*
 167 * When 1, {\tt ebreak} instructions in User/Application Mode enter
 168 * Halt Mode.
 169  */
 170 #define CSR_DCSR_EBREAKU_OFFSET             12
 171 #define CSR_DCSR_EBREAKU_LENGTH             1
 172 #define CSR_DCSR_EBREAKU                    (0x1 << CSR_DCSR_EBREAKU_OFFSET)
 173 /*
 174 * 0: Increment counters as usual.
 175 *
 176 * 1: Don't increment any counters while in Halt Mode.  This includes
 177 * the {\tt cycle} and {\tt instret} CSRs. This is preferred for most
 178 * debugging scenarios.
 179 *
 180 * An implementation may choose not to support writing to this bit.
 181 * The debugger must read back the value it writes to check whether
 182 * the feature is supported.
 183  */
 184 #define CSR_DCSR_STOPCOUNT_OFFSET           10
 185 #define CSR_DCSR_STOPCOUNT_LENGTH           1
 186 #define CSR_DCSR_STOPCOUNT                  (0x1 << CSR_DCSR_STOPCOUNT_OFFSET)
 187 /*
 188 * 0: Increment timers as usual.
 189 *
 190 * 1: Don't increment any hart-local timers while in Halt Mode.
 191 *
 192 * An implementation may choose not to support writing to this bit.
 193 * The debugger must read back the value it writes to check whether
 194 * the feature is supported.
 195  */
 196 #define CSR_DCSR_STOPTIME_OFFSET            9
 197 #define CSR_DCSR_STOPTIME_LENGTH            1
 198 #define CSR_DCSR_STOPTIME                   (0x1 << CSR_DCSR_STOPTIME_OFFSET)
 199 /*
 200 * Explains why Halt Mode was entered.
 201 *
 202 * When there are multiple reasons to enter Halt Mode in a single
 203 * cycle, the cause with the highest priority is the one written.
 204 *
 205 * 1: A software breakpoint was hit. (priority 3)
 206 *
 207 * 2: The Trigger Module caused a halt. (priority 4)
 208 *
 209 * 3: The debug interrupt was asserted by the Debug Module. (priority 2)
 210 *
 211 * 4: The hart single stepped because \Fstep was set. (priority 1)
 212 *
 213 * 5: \Fhaltreq was set. (priority 0)
 214 *
 215 * Other values are reserved for future use.
 216  */
 217 #define CSR_DCSR_CAUSE_OFFSET               6
 218 #define CSR_DCSR_CAUSE_LENGTH               3
 219 #define CSR_DCSR_CAUSE                      (0x7 << CSR_DCSR_CAUSE_OFFSET)
 220 /*
 221 * When set and not in Halt Mode, the hart will only execute a single
 222 * instruction, and then enter Halt Mode. Interrupts are disabled
 223 * when this bit is set.
 224  */
 225 #define CSR_DCSR_STEP_OFFSET                2
 226 #define CSR_DCSR_STEP_LENGTH                1
 227 #define CSR_DCSR_STEP                       (0x1 << CSR_DCSR_STEP_OFFSET)
 228 /*
 229 * Contains the privilege level the hart was operating in when Debug
 230 * Mode was entered. The encoding is describe in Table
 231 * \ref{tab:privlevel}.  A debugger can change this value to change
 232 * the hart's privilege level when exiting Halt Mode.
 233 *
 234 * Not all privilege levels are supported on all harts. If the
 235 * encoding written is not supported or the debugger is not allowed to
 236 * change to it, the hart may change to any supported privilege level.
 237  */
 238 #define CSR_DCSR_PRV_OFFSET                 0
 239 #define CSR_DCSR_PRV_LENGTH                 2
 240 #define CSR_DCSR_PRV                        (0x3 << CSR_DCSR_PRV_OFFSET)
 241 #define CSR_DPC                             0x7b1
 242 #define CSR_DPC_DPC_OFFSET                  0
 243 #define CSR_DPC_DPC_LENGTH                  XLEN
 244 #define CSR_DPC_DPC                         (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
 245 #define CSR_DSCRATCH0                       0x7b2
 246 #define CSR_DSCRATCH1                       0x7b3
 247 #define CSR_PRIV                            virtual
 248 /*
 249 * Contains the privilege level the hart was operating in when Debug
 250 * Mode was entered. The encoding is describe in Table
 251 * \ref{tab:privlevel}. A user can write this value to change the
 252 * hart's privilege level when exiting Halt Mode.
 253  */
 254 #define CSR_PRIV_PRV_OFFSET                 0
 255 #define CSR_PRIV_PRV_LENGTH                 2
 256 #define CSR_PRIV_PRV                        (0x3 << CSR_PRIV_PRV_OFFSET)
 257 #define CSR_TSELECT                         0x7a0
 258 #define CSR_TSELECT_INDEX_OFFSET            0
 259 #define CSR_TSELECT_INDEX_LENGTH            XLEN
 260 #define CSR_TSELECT_INDEX                   (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
 261 #define CSR_TDATA1                          0x7a1
 262 /*
 263 * 0: There is no trigger at this \Rtselect.
 264 *
 265 * 1: The trigger is a legacy SiFive address match trigger. These
 266 * should not be implemented and aren't further documented here.
 267 *
 268 * 2: The trigger is an address/data match trigger. The remaining bits
 269 * in this register act as described in \Rmcontrol.
 270 *
 271 * 3: The trigger is an instruction count trigger. The remaining bits
 272 * in this register act as described in \Ricount.
 273 *
 274 * 15: This trigger exists (so enumeration shouldn't terminate), but
 275 * is not currently available.
 276 *
 277 * Other values are reserved for future use.
 278  */
 279 #define CSR_TDATA1_TYPE_OFFSET              XLEN-4
 280 #define CSR_TDATA1_TYPE_LENGTH              4
 281 #define CSR_TDATA1_TYPE                     (0xfL << CSR_TDATA1_TYPE_OFFSET)
 282 /*
 283 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the
 284 * selected \Rtselect.
 285 *
 286 * 1: Only Halt Mode can write the {\tt tdata} registers at the
 287 * selected \Rtselect.  Writes from other modes are ignored.
 288 *
 289 * This bit is only writable from Halt Mode.
 290  */
 291 #define CSR_TDATA1_HMODE_OFFSET             XLEN-5
 292 #define CSR_TDATA1_HMODE_LENGTH             1
 293 #define CSR_TDATA1_HMODE                    (0x1L << CSR_TDATA1_HMODE_OFFSET)
 294 /*
 295 * Trigger-specific data.
 296  */
 297 #define CSR_TDATA1_DATA_OFFSET              0
 298 #define CSR_TDATA1_DATA_LENGTH              XLEN - 5
 299 #define CSR_TDATA1_DATA                     (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
 300 #define CSR_TDATA2                          0x7a2
 301 #define CSR_TDATA2_DATA_OFFSET              0
 302 #define CSR_TDATA2_DATA_LENGTH              XLEN
 303 #define CSR_TDATA2_DATA                     (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET)
 304 #define CSR_TDATA3                          0x7a3
 305 #define CSR_TDATA3_DATA_OFFSET              0
 306 #define CSR_TDATA3_DATA_LENGTH              XLEN
 307 #define CSR_TDATA3_DATA                     (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET)
 308 #define CSR_MCONTROL                        0x7a1
 309 #define CSR_MCONTROL_TYPE_OFFSET            XLEN-4
 310 #define CSR_MCONTROL_TYPE_LENGTH            4
 311 #define CSR_MCONTROL_TYPE                   (0xfL << CSR_MCONTROL_TYPE_OFFSET)
 312 #define CSR_MCONTROL_DMODE_OFFSET           XLEN-5
 313 #define CSR_MCONTROL_DMODE_LENGTH           1
 314 #define CSR_MCONTROL_DMODE                  (0x1L << CSR_MCONTROL_DMODE_OFFSET)
 315 /*
 316 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
 317 * supported by the hardware. The value is the logarithm base 2 of the
 318 * number of bytes in that range.  A value of 0 indicates that only
 319 * exact value matches are supported (one byte range). A value of 63
 320 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
 321 * size.
 322  */
 323 #define CSR_MCONTROL_MASKMAX_OFFSET         XLEN-11
 324 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 325 #define CSR_MCONTROL_MASKMAX                (0x3fL << CSR_MCONTROL_MASKMAX_OFFSET)
 326 /*
 327 * 0: Perform a match on the virtual address.
 328 *
 329 * 1: Perform a match on the data value loaded/stored, or the
 330 * instruction executed.
 331  */
 332 #define CSR_MCONTROL_SELECT_OFFSET          19
 333 #define CSR_MCONTROL_SELECT_LENGTH          1
 334 #define CSR_MCONTROL_SELECT                 (0x1L << CSR_MCONTROL_SELECT_OFFSET)
 335 /*
 336 * 0: The action for this trigger will be taken just before the
 337 * instruction that triggered it is executed, but after all preceding
 338 * instructions are are committed.
 339 *
 340 * 1: The action for this trigger will be taken after the instruction
 341 * that triggered it is executed. It should be taken before the next
 342 * instruction is executed, but it is better to implement triggers and
 343 * not implement that suggestion than to not implement them at all.
 344 *
 345 * Most hardware will only implement one timing or the other, possibly
 346 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
 347 * primarily exists for the hardware to communicate to the debugger
 348 * what will happen. Hardware may implement the bit fully writable, in
 349 * which case the debugger has a little more control.
 350 *
 351 * Data load triggers with \Ftiming of 0 will result in the same load
 352 * happening again when the debugger lets the core run. For data load
 353 * triggers, debuggers must first attempt to set the breakpoint with
 354 * \Ftiming of 1.
 355 *
 356 * A chain of triggers that don't all have the same \Ftiming value
 357 * will never fire (unless consecutive instructions match the
 358 * appropriate triggers).
 359  */
 360 #define CSR_MCONTROL_TIMING_OFFSET          18
 361 #define CSR_MCONTROL_TIMING_LENGTH          1
 362 #define CSR_MCONTROL_TIMING                 (0x1L << CSR_MCONTROL_TIMING_OFFSET)
 363 /*
 364 * Determines what happens when this trigger matches.
 365 *
 366 * 0: Raise a breakpoint exception. (Used when software wants to use
 367 * the trigger module without an external debugger attached.)
 368 *
 369 * 1: Enter Halt Mode. (Only supported when \Fhmode is 1.)
 370 *
 371 * 2: Start tracing.
 372 *
 373 * 3: Stop tracing.
 374 *
 375 * 4: Emit trace data for this match. If it is a data access match,
 376 * emit appropriate Load/Store Address/Data. If it is an instruction
 377 * execution, emit its PC.
 378 *
 379 * Other values are reserved for future use.
 380  */
 381 #define CSR_MCONTROL_ACTION_OFFSET          12
 382 #define CSR_MCONTROL_ACTION_LENGTH          6
 383 #define CSR_MCONTROL_ACTION                 (0x3fL << CSR_MCONTROL_ACTION_OFFSET)
 384 /*
 385 * 0: When this trigger matches, the configured action is taken.
 386 *
 387 * 1: While this trigger does not match, it prevents the trigger with
 388 * the next index from matching.
 389  */
 390 #define CSR_MCONTROL_CHAIN_OFFSET           11
 391 #define CSR_MCONTROL_CHAIN_LENGTH           1
 392 #define CSR_MCONTROL_CHAIN                  (0x1L << CSR_MCONTROL_CHAIN_OFFSET)
 393 /*
 394 * 0: Matches when the value equals \Rtdatatwo.
 395 *
 396 * 1: Matches when the top M bits of the value match the top M bits of
 397 * \Rtdatatwo. M is XLEN-1 minus the index of the least-significant
 398 * bit containing 0 in \Rtdatatwo.
 399 *
 400 * 2: Matches when the value is greater than or equal to \Rtdatatwo.
 401 *
 402 * 3: Matches when the value is less than \Rtdatatwo.
 403 *
 404 * 4: Matches when the lower half of the value equals the lower half
 405 * of \Rtdatatwo after the lower half of the value is ANDed with the
 406 * upper half of \Rtdatatwo.
 407 *
 408 * 5: Matches when the upper half of the value equals the lower half
 409 * of \Rtdatatwo after the upper half of the value is ANDed with the
 410 * upper half of \Rtdatatwo.
 411 *
 412 * Other values are reserved for future use.
 413  */
 414 #define CSR_MCONTROL_MATCH_OFFSET           7
 415 #define CSR_MCONTROL_MATCH_LENGTH           4
 416 #define CSR_MCONTROL_MATCH                  (0xfL << CSR_MCONTROL_MATCH_OFFSET)
 417 /*
 418 * When set, enable this trigger in M mode.
 419  */
 420 #define CSR_MCONTROL_M_OFFSET               6
 421 #define CSR_MCONTROL_M_LENGTH               1
 422 #define CSR_MCONTROL_M                      (0x1L << CSR_MCONTROL_M_OFFSET)
 423 /*
 424 * When set, enable this trigger in H mode.
 425  */
 426 #define CSR_MCONTROL_H_OFFSET               5
 427 #define CSR_MCONTROL_H_LENGTH               1
 428 #define CSR_MCONTROL_H                      (0x1L << CSR_MCONTROL_H_OFFSET)
 429 /*
 430 * When set, enable this trigger in S mode.
 431  */
 432 #define CSR_MCONTROL_S_OFFSET               4
 433 #define CSR_MCONTROL_S_LENGTH               1
 434 #define CSR_MCONTROL_S                      (0x1L << CSR_MCONTROL_S_OFFSET)
 435 /*
 436 * When set, enable this trigger in U mode.
 437  */
 438 #define CSR_MCONTROL_U_OFFSET               3
 439 #define CSR_MCONTROL_U_LENGTH               1
 440 #define CSR_MCONTROL_U                      (0x1L << CSR_MCONTROL_U_OFFSET)
 441 /*
 442 * When set, the trigger fires on the virtual address or opcode of an
 443 * instruction that is executed.
 444  */
 445 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 446 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 447 #define CSR_MCONTROL_EXECUTE                (0x1L << CSR_MCONTROL_EXECUTE_OFFSET)
 448 /*
 449 * When set, the trigger fires on the virtual address or data of a store.
 450  */
 451 #define CSR_MCONTROL_STORE_OFFSET           1
 452 #define CSR_MCONTROL_STORE_LENGTH           1
 453 #define CSR_MCONTROL_STORE                  (0x1L << CSR_MCONTROL_STORE_OFFSET)
 454 /*
 455 * When set, the trigger fires on the virtual address or data of a load.
 456  */
 457 #define CSR_MCONTROL_LOAD_OFFSET            0
 458 #define CSR_MCONTROL_LOAD_LENGTH            1
 459 #define CSR_MCONTROL_LOAD                   (0x1L << CSR_MCONTROL_LOAD_OFFSET)
 460 #define CSR_ICOUNT                          0x7a1
 461 #define CSR_ICOUNT_TYPE_OFFSET              XLEN-4
 462 #define CSR_ICOUNT_TYPE_LENGTH              4
 463 #define CSR_ICOUNT_TYPE                     (0xfL << CSR_ICOUNT_TYPE_OFFSET)
 464 #define CSR_ICOUNT_DMODE_OFFSET             XLEN-5
 465 #define CSR_ICOUNT_DMODE_LENGTH             1
 466 #define CSR_ICOUNT_DMODE                    (0x1L << CSR_ICOUNT_DMODE_OFFSET)
 467 /*
 468 * When count is decremented to 0, the trigger fires. Instead of
 469 * changing \Fcount from 1 to 0, it is also acceptable for hardware to
 470 * clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired
 471 * to 1 if this register just exists for single step.
 472  */
 473 #define CSR_ICOUNT_COUNT_OFFSET             10
 474 #define CSR_ICOUNT_COUNT_LENGTH             14
 475 #define CSR_ICOUNT_COUNT                    (0x3fffL << CSR_ICOUNT_COUNT_OFFSET)
 476 /*
 477 * When set, every instruction completed in M mode decrements \Fcount
 478 * by 1.
 479  */
 480 #define CSR_ICOUNT_M_OFFSET                 9
 481 #define CSR_ICOUNT_M_LENGTH                 1
 482 #define CSR_ICOUNT_M                        (0x1L << CSR_ICOUNT_M_OFFSET)
 483 /*
 484 * When set, every instruction completed in H mode decrements \Fcount
 485 * by 1.
 486  */
 487 #define CSR_ICOUNT_H_OFFSET                 8
 488 #define CSR_ICOUNT_H_LENGTH                 1
 489 #define CSR_ICOUNT_H                        (0x1L << CSR_ICOUNT_H_OFFSET)
 490 /*
 491 * When set, every instruction completed in S mode decrements \Fcount
 492 * by 1.
 493  */
 494 #define CSR_ICOUNT_S_OFFSET                 7
 495 #define CSR_ICOUNT_S_LENGTH                 1
 496 #define CSR_ICOUNT_S                        (0x1L << CSR_ICOUNT_S_OFFSET)
 497 /*
 498 * When set, every instruction completed in U mode decrements \Fcount
 499 * by 1.
 500  */
 501 #define CSR_ICOUNT_U_OFFSET                 6
 502 #define CSR_ICOUNT_U_LENGTH                 1
 503 #define CSR_ICOUNT_U                        (0x1L << CSR_ICOUNT_U_OFFSET)
 504 /*
 505 * Determines what happens when this trigger matches.
 506 *
 507 * 0: Raise a debug exception. (Used when software wants to use the
 508 * trigger module without an external debugger attached.)
 509 *
 510 * 1: Enter Halt Mode. (Only supported when \Fhmode is 1.)
 511 *
 512 * 2: Start tracing.
 513 *
 514 * 3: Stop tracing.
 515 *
 516 * 4: Emit trace data for this match. If it is a data access match,
 517 * emit appropriate Load/Store Address/Data. If it is an instruction
 518 * execution, emit its PC.
 519 *
 520 * Other values are reserved for future use.
 521  */
 522 #define CSR_ICOUNT_ACTION_OFFSET            0
 523 #define CSR_ICOUNT_ACTION_LENGTH            6
 524 #define CSR_ICOUNT_ACTION                   (0x3fL << CSR_ICOUNT_ACTION_OFFSET)
 525 #define DMI_DMSTATUS                        0x11
 526 /*
 527 * This field is 1 when all currently selected harts do not exist in this system.
 528  */
 529 #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET  15
 530 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH  1
 531 #define DMI_DMSTATUS_ALLNONEXISTENT         (0x1 << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET)
 532 /*
 533 * This field is 1 when any currently selected hart does not exist in this system.
 534  */
 535 #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET  14
 536 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH  1
 537 #define DMI_DMSTATUS_ANYNONEXISTENT         (0x1 << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET)
 538 /*
 539 * This field is 1 when all currently selected harts are unavailable.
 540  */
 541 #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET      13
 542 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH      1
 543 #define DMI_DMSTATUS_ALLUNAVAIL             (0x1 << DMI_DMSTATUS_ALLUNAVAIL_OFFSET)
 544 /*
 545 * This field is 1 when any currently selected hart is unavailable.
 546  */
 547 #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET      12
 548 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH      1
 549 #define DMI_DMSTATUS_ANYUNAVAIL             (0x1 << DMI_DMSTATUS_ANYUNAVAIL_OFFSET)
 550 /*
 551 * This field is 1 when all currently selected harts are running.
 552  */
 553 #define DMI_DMSTATUS_ALLRUNNING_OFFSET      11
 554 #define DMI_DMSTATUS_ALLRUNNING_LENGTH      1
 555 #define DMI_DMSTATUS_ALLRUNNING             (0x1 << DMI_DMSTATUS_ALLRUNNING_OFFSET)
 556 /*
 557 * This field is 1 when any currently selected hart is running.
 558  */
 559 #define DMI_DMSTATUS_ANYRUNNING_OFFSET      10
 560 #define DMI_DMSTATUS_ANYRUNNING_LENGTH      1
 561 #define DMI_DMSTATUS_ANYRUNNING             (0x1 << DMI_DMSTATUS_ANYRUNNING_OFFSET)
 562 /*
 563 * This field is 1 when all currently selected harts are halted.
 564  */
 565 #define DMI_DMSTATUS_ALLHALTED_OFFSET       9
 566 #define DMI_DMSTATUS_ALLHALTED_LENGTH       1
 567 #define DMI_DMSTATUS_ALLHALTED              (0x1 << DMI_DMSTATUS_ALLHALTED_OFFSET)
 568 /*
 569 * This field is 1 when any currently selected hart is halted.
 570  */
 571 #define DMI_DMSTATUS_ANYHALTED_OFFSET       8
 572 #define DMI_DMSTATUS_ANYHALTED_LENGTH       1
 573 #define DMI_DMSTATUS_ANYHALTED              (0x1 << DMI_DMSTATUS_ANYHALTED_OFFSET)
 574 /*
 575 * 0 when authentication is required before using the DM.  1 when the
 576 * authentication check has passed. On components that don't implement
 577 * authentication, this bit must be preset as 1.
 578  */
 579 #define DMI_DMSTATUS_AUTHENTICATED_OFFSET   7
 580 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH   1
 581 #define DMI_DMSTATUS_AUTHENTICATED          (0x1 << DMI_DMSTATUS_AUTHENTICATED_OFFSET)
 582 /*
 583 * 0: The authentication module is ready to process the next
 584 * read/write to \Rauthdata.
 585 *
 586 * 1: The authentication module is busy. Accessing \Rauthdata results
 587 * in unspecified behavior.
 588 *
 589 * \Fauthbusy only becomes set in immediate response to an access to
 590 * \Rauthdata.
 591  */
 592 #define DMI_DMSTATUS_AUTHBUSY_OFFSET        6
 593 #define DMI_DMSTATUS_AUTHBUSY_LENGTH        1
 594 #define DMI_DMSTATUS_AUTHBUSY               (0x1 << DMI_DMSTATUS_AUTHBUSY_OFFSET)
 595 #define DMI_DMSTATUS_CFGSTRVALID_OFFSET     4
 596 #define DMI_DMSTATUS_CFGSTRVALID_LENGTH     1
 597 #define DMI_DMSTATUS_CFGSTRVALID            (0x1 << DMI_DMSTATUS_CFGSTRVALID_OFFSET)
 598 /*
 599 * Reserved for future use. Reads as 0.
 600  */
 601 #define DMI_DMSTATUS_VERSIONHI_OFFSET       2
 602 #define DMI_DMSTATUS_VERSIONHI_LENGTH       2
 603 #define DMI_DMSTATUS_VERSIONHI              (0x3 << DMI_DMSTATUS_VERSIONHI_OFFSET)
 604 /*
 605 * 00: There is no Debug Module present.
 606 *
 607 * 01: There is a Debug Module and it conforms to version 0.11 of this
 608 * specification.
 609 *
 610 * 10: There is a Debug Module and it conforms to version 0.13 of this
 611 * specification.
 612 *
 613 * 11: Reserved for future use.
 614  */
 615 #define DMI_DMSTATUS_VERSIONLO_OFFSET       0
 616 #define DMI_DMSTATUS_VERSIONLO_LENGTH       2
 617 #define DMI_DMSTATUS_VERSIONLO              (0x3 << DMI_DMSTATUS_VERSIONLO_OFFSET)
 618 #define DMI_DMCONTROL                       0x10
 619 /*
 620 * Halt request signal for all currently selected harts. When 1, the
 621 * hart will halt if it is not currently halted.
 622 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 623 *
 624 * Writes apply to the new value of \Fhartsel and \Fhasel.
 625  */
 626 #define DMI_DMCONTROL_HALTREQ_OFFSET        31
 627 #define DMI_DMCONTROL_HALTREQ_LENGTH        1
 628 #define DMI_DMCONTROL_HALTREQ               (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET)
 629 /*
 630 * Resume request signal for all currently selected harts. When 1,
 631 * the hart will resume if it is currently halted.
 632 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 633 *
 634 * Writes apply to the new value of \Fhartsel and \Fhasel.
 635  */
 636 #define DMI_DMCONTROL_RESUMEREQ_OFFSET      30
 637 #define DMI_DMCONTROL_RESUMEREQ_LENGTH      1
 638 #define DMI_DMCONTROL_RESUMEREQ             (0x1 << DMI_DMCONTROL_RESUMEREQ_OFFSET)
 639 /*
 640 * This optional bit controls reset to all the currently selected harts.
 641 * To perform a reset the debugger writes 1, and then writes 0 to
 642 * deassert the reset signal.
 643 *
 644 * If this feature is not implemented, the bit always stays 0, so
 645 * after writing 1 the debugger can read the register back to see if
 646 * the feature is supported.
 647 *
 648 * Writes apply to the new value of \Fhartsel and \Fhasel.
 649  */
 650 #define DMI_DMCONTROL_HARTRESET_OFFSET      29
 651 #define DMI_DMCONTROL_HARTRESET_LENGTH      1
 652 #define DMI_DMCONTROL_HARTRESET             (0x1 << DMI_DMCONTROL_HARTRESET_OFFSET)
 653 /*
 654 * Selects the  definition of currently selected harts.
 655 *
 656 * 0: There is a single currently selected hart, that selected by \Fhartsel.
 657 *
 658 * 1: There may be multiple currently selected harts -- that selected by \Fhartsel,
 659 * plus those selected by the hart array mask register.
 660 *
 661 * An implementation which does not implement the hart array mask register
 662 * should tie this field to 0. A debugger which wishes to use the hart array
 663 * mask register feature should set this bit and read back to see if the functionality
 664 * is supported.
 665  */
 666 #define DMI_DMCONTROL_HASEL_OFFSET          26
 667 #define DMI_DMCONTROL_HASEL_LENGTH          1
 668 #define DMI_DMCONTROL_HASEL                 (0x1 << DMI_DMCONTROL_HASEL_OFFSET)
 669 /*
 670 * The DM-specific index of the hart to select. This hart is always part of the
 671 * currently selected harts.
 672  */
 673 #define DMI_DMCONTROL_HARTSEL_OFFSET        16
 674 #define DMI_DMCONTROL_HARTSEL_LENGTH        10
 675 #define DMI_DMCONTROL_HARTSEL               (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET)
 676 /*
 677 * This bit controls the reset signal from the DM to the rest of the
 678 * system. To perform a reset the debugger writes 1, and then writes 0
 679 * to deassert the reset.
 680  */
 681 #define DMI_DMCONTROL_NDMRESET_OFFSET       1
 682 #define DMI_DMCONTROL_NDMRESET_LENGTH       1
 683 #define DMI_DMCONTROL_NDMRESET              (0x1 << DMI_DMCONTROL_NDMRESET_OFFSET)
 684 /*
 685 * This bit serves as a reset signal for the Debug Module itself.
 686 *
 687 * 0: The module's state, including authentication mechanism,
 688 * takes its reset values (the \Fdmactive bit is the only bit which can
 689 * be written to something other than its reset value).
 690 *
 691 * 1: The module functions normally.
 692 *
 693 * No other mechanism should exist that may result in resetting the
 694 * Debug Module after power up, including the platform's system reset
 695 * or Debug Transport reset signals.
 696 *
 697 * A debugger should pulse this bit low to ensure that the Debug
 698 * Module is fully reset and ready to use.
 699 *
 700 * Implementations may use this bit to aid debugging, for example by
 701 * preventing the Debug Module from being power gated while debugging
 702 * is active.
 703  */
 704 #define DMI_DMCONTROL_DMACTIVE_OFFSET       0
 705 #define DMI_DMCONTROL_DMACTIVE_LENGTH       1
 706 #define DMI_DMCONTROL_DMACTIVE              (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET)
 707 #define DMI_HARTINFO                        0x12
 708 /*
 709 * Number of {\tt dscratch} registers available for the debugger
 710 * to use during program buffer execution, starting from \Rdscratchzero.
 711 * The debugger can make no assumptions about the contents of these
 712 * registers between commands.
 713  */
 714 #define DMI_HARTINFO_NSCRATCH_OFFSET        20
 715 #define DMI_HARTINFO_NSCRATCH_LENGTH        4
 716 #define DMI_HARTINFO_NSCRATCH               (0xf << DMI_HARTINFO_NSCRATCH_OFFSET)
 717 /*
 718 * 0: The {\tt data} registers are shadowed in the hart by CSR
 719 * registers. Each CSR register is XLEN bits in size, and corresponds
 720 * to a single argument, per Table~\ref{tab:datareg}.
 721 *
 722 * 1: The {\tt data} registers are shadowed in the hart's memory map.
 723 * Each register takes up 4 bytes in the memory map.
 724  */
 725 #define DMI_HARTINFO_DATAACCESS_OFFSET      16
 726 #define DMI_HARTINFO_DATAACCESS_LENGTH      1
 727 #define DMI_HARTINFO_DATAACCESS             (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET)
 728 /*
 729 * If \Fdataaccess is 0: Number of CSR registers dedicated to
 730 * shadowing the {\tt data} registers.
 731 *
 732 * If \Fdataaccess is 1: Number of 32-bit words in the memory map
 733 * dedicated to shadowing the {\tt data} registers.
 734  */
 735 #define DMI_HARTINFO_DATASIZE_OFFSET        12
 736 #define DMI_HARTINFO_DATASIZE_LENGTH        4
 737 #define DMI_HARTINFO_DATASIZE               (0xf << DMI_HARTINFO_DATASIZE_OFFSET)
 738 /*
 739 * If \Fdataaccess is 0: The number of the first CSR dedicated to
 740 * shadowing the {\tt data} registers.
 741 *
 742 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
 743 * registers are shadowed.
 744  */
 745 #define DMI_HARTINFO_DATAADDR_OFFSET        0
 746 #define DMI_HARTINFO_DATAADDR_LENGTH        12
 747 #define DMI_HARTINFO_DATAADDR               (0xfff << DMI_HARTINFO_DATAADDR_OFFSET)
 748 #define DMI_HALTSUM                         0x13
 749 #define DMI_HALTSUM_HALT1023_992_OFFSET     31
 750 #define DMI_HALTSUM_HALT1023_992_LENGTH     1
 751 #define DMI_HALTSUM_HALT1023_992            (0x1 << DMI_HALTSUM_HALT1023_992_OFFSET)
 752 #define DMI_HALTSUM_HALT991_960_OFFSET      30
 753 #define DMI_HALTSUM_HALT991_960_LENGTH      1
 754 #define DMI_HALTSUM_HALT991_960             (0x1 << DMI_HALTSUM_HALT991_960_OFFSET)
 755 #define DMI_HALTSUM_HALT959_928_OFFSET      29
 756 #define DMI_HALTSUM_HALT959_928_LENGTH      1
 757 #define DMI_HALTSUM_HALT959_928             (0x1 << DMI_HALTSUM_HALT959_928_OFFSET)
 758 #define DMI_HALTSUM_HALT927_896_OFFSET      28
 759 #define DMI_HALTSUM_HALT927_896_LENGTH      1
 760 #define DMI_HALTSUM_HALT927_896             (0x1 << DMI_HALTSUM_HALT927_896_OFFSET)
 761 #define DMI_HALTSUM_HALT895_864_OFFSET      27
 762 #define DMI_HALTSUM_HALT895_864_LENGTH      1
 763 #define DMI_HALTSUM_HALT895_864             (0x1 << DMI_HALTSUM_HALT895_864_OFFSET)
 764 #define DMI_HALTSUM_HALT863_832_OFFSET      26
 765 #define DMI_HALTSUM_HALT863_832_LENGTH      1
 766 #define DMI_HALTSUM_HALT863_832             (0x1 << DMI_HALTSUM_HALT863_832_OFFSET)
 767 #define DMI_HALTSUM_HALT831_800_OFFSET      25
 768 #define DMI_HALTSUM_HALT831_800_LENGTH      1
 769 #define DMI_HALTSUM_HALT831_800             (0x1 << DMI_HALTSUM_HALT831_800_OFFSET)
 770 #define DMI_HALTSUM_HALT799_768_OFFSET      24
 771 #define DMI_HALTSUM_HALT799_768_LENGTH      1
 772 #define DMI_HALTSUM_HALT799_768             (0x1 << DMI_HALTSUM_HALT799_768_OFFSET)
 773 #define DMI_HALTSUM_HALT767_736_OFFSET      23
 774 #define DMI_HALTSUM_HALT767_736_LENGTH      1
 775 #define DMI_HALTSUM_HALT767_736             (0x1 << DMI_HALTSUM_HALT767_736_OFFSET)
 776 #define DMI_HALTSUM_HALT735_704_OFFSET      22
 777 #define DMI_HALTSUM_HALT735_704_LENGTH      1
 778 #define DMI_HALTSUM_HALT735_704             (0x1 << DMI_HALTSUM_HALT735_704_OFFSET)
 779 #define DMI_HALTSUM_HALT703_672_OFFSET      21
 780 #define DMI_HALTSUM_HALT703_672_LENGTH      1
 781 #define DMI_HALTSUM_HALT703_672             (0x1 << DMI_HALTSUM_HALT703_672_OFFSET)
 782 #define DMI_HALTSUM_HALT671_640_OFFSET      20
 783 #define DMI_HALTSUM_HALT671_640_LENGTH      1
 784 #define DMI_HALTSUM_HALT671_640             (0x1 << DMI_HALTSUM_HALT671_640_OFFSET)
 785 #define DMI_HALTSUM_HALT639_608_OFFSET      19
 786 #define DMI_HALTSUM_HALT639_608_LENGTH      1
 787 #define DMI_HALTSUM_HALT639_608             (0x1 << DMI_HALTSUM_HALT639_608_OFFSET)
 788 #define DMI_HALTSUM_HALT607_576_OFFSET      18
 789 #define DMI_HALTSUM_HALT607_576_LENGTH      1
 790 #define DMI_HALTSUM_HALT607_576             (0x1 << DMI_HALTSUM_HALT607_576_OFFSET)
 791 #define DMI_HALTSUM_HALT575_544_OFFSET      17
 792 #define DMI_HALTSUM_HALT575_544_LENGTH      1
 793 #define DMI_HALTSUM_HALT575_544             (0x1 << DMI_HALTSUM_HALT575_544_OFFSET)
 794 #define DMI_HALTSUM_HALT543_512_OFFSET      16
 795 #define DMI_HALTSUM_HALT543_512_LENGTH      1
 796 #define DMI_HALTSUM_HALT543_512             (0x1 << DMI_HALTSUM_HALT543_512_OFFSET)
 797 #define DMI_HALTSUM_HALT511_480_OFFSET      15
 798 #define DMI_HALTSUM_HALT511_480_LENGTH      1
 799 #define DMI_HALTSUM_HALT511_480             (0x1 << DMI_HALTSUM_HALT511_480_OFFSET)
 800 #define DMI_HALTSUM_HALT479_448_OFFSET      14
 801 #define DMI_HALTSUM_HALT479_448_LENGTH      1
 802 #define DMI_HALTSUM_HALT479_448             (0x1 << DMI_HALTSUM_HALT479_448_OFFSET)
 803 #define DMI_HALTSUM_HALT447_416_OFFSET      13
 804 #define DMI_HALTSUM_HALT447_416_LENGTH      1
 805 #define DMI_HALTSUM_HALT447_416             (0x1 << DMI_HALTSUM_HALT447_416_OFFSET)
 806 #define DMI_HALTSUM_HALT415_384_OFFSET      12
 807 #define DMI_HALTSUM_HALT415_384_LENGTH      1
 808 #define DMI_HALTSUM_HALT415_384             (0x1 << DMI_HALTSUM_HALT415_384_OFFSET)
 809 #define DMI_HALTSUM_HALT383_352_OFFSET      11
 810 #define DMI_HALTSUM_HALT383_352_LENGTH      1
 811 #define DMI_HALTSUM_HALT383_352             (0x1 << DMI_HALTSUM_HALT383_352_OFFSET)
 812 #define DMI_HALTSUM_HALT351_320_OFFSET      10
 813 #define DMI_HALTSUM_HALT351_320_LENGTH      1
 814 #define DMI_HALTSUM_HALT351_320             (0x1 << DMI_HALTSUM_HALT351_320_OFFSET)
 815 #define DMI_HALTSUM_HALT319_288_OFFSET      9
 816 #define DMI_HALTSUM_HALT319_288_LENGTH      1
 817 #define DMI_HALTSUM_HALT319_288             (0x1 << DMI_HALTSUM_HALT319_288_OFFSET)
 818 #define DMI_HALTSUM_HALT287_256_OFFSET      8
 819 #define DMI_HALTSUM_HALT287_256_LENGTH      1
 820 #define DMI_HALTSUM_HALT287_256             (0x1 << DMI_HALTSUM_HALT287_256_OFFSET)
 821 #define DMI_HALTSUM_HALT255_224_OFFSET      7
 822 #define DMI_HALTSUM_HALT255_224_LENGTH      1
 823 #define DMI_HALTSUM_HALT255_224             (0x1 << DMI_HALTSUM_HALT255_224_OFFSET)
 824 #define DMI_HALTSUM_HALT223_192_OFFSET      6
 825 #define DMI_HALTSUM_HALT223_192_LENGTH      1
 826 #define DMI_HALTSUM_HALT223_192             (0x1 << DMI_HALTSUM_HALT223_192_OFFSET)
 827 #define DMI_HALTSUM_HALT191_160_OFFSET      5
 828 #define DMI_HALTSUM_HALT191_160_LENGTH      1
 829 #define DMI_HALTSUM_HALT191_160             (0x1 << DMI_HALTSUM_HALT191_160_OFFSET)
 830 #define DMI_HALTSUM_HALT159_128_OFFSET      4
 831 #define DMI_HALTSUM_HALT159_128_LENGTH      1
 832 #define DMI_HALTSUM_HALT159_128             (0x1 << DMI_HALTSUM_HALT159_128_OFFSET)
 833 #define DMI_HALTSUM_HALT127_96_OFFSET       3
 834 #define DMI_HALTSUM_HALT127_96_LENGTH       1
 835 #define DMI_HALTSUM_HALT127_96              (0x1 << DMI_HALTSUM_HALT127_96_OFFSET)
 836 #define DMI_HALTSUM_HALT95_64_OFFSET        2
 837 #define DMI_HALTSUM_HALT95_64_LENGTH        1
 838 #define DMI_HALTSUM_HALT95_64               (0x1 << DMI_HALTSUM_HALT95_64_OFFSET)
 839 #define DMI_HALTSUM_HALT63_32_OFFSET        1
 840 #define DMI_HALTSUM_HALT63_32_LENGTH        1
 841 #define DMI_HALTSUM_HALT63_32               (0x1 << DMI_HALTSUM_HALT63_32_OFFSET)
 842 #define DMI_HALTSUM_HALT31_0_OFFSET         0
 843 #define DMI_HALTSUM_HALT31_0_LENGTH         1
 844 #define DMI_HALTSUM_HALT31_0                (0x1 << DMI_HALTSUM_HALT31_0_OFFSET)
 845 #define DMI_HAWINDOWSEL                     0x14
 846 #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET  0
 847 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH  5
 848 #define DMI_HAWINDOWSEL_HAWINDOWSEL         (0x1f << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
 849 #define DMI_HAWINDOW                        0x15
 850 #define DMI_HAWINDOW_MASKDATA_OFFSET        0
 851 #define DMI_HAWINDOW_MASKDATA_LENGTH        32
 852 #define DMI_HAWINDOW_MASKDATA               (0xffffffff << DMI_HAWINDOW_MASKDATA_OFFSET)
 853 #define DMI_ABSTRACTCS                      0x16
 854 /*
 855 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
 856 *
 857 * TODO: Explain what can be done with each size of the buffer, to suggest
 858 * why you would want more or less words.
 859  */
 860 #define DMI_ABSTRACTCS_PROGSIZE_OFFSET      24
 861 #define DMI_ABSTRACTCS_PROGSIZE_LENGTH      5
 862 #define DMI_ABSTRACTCS_PROGSIZE             (0x1f << DMI_ABSTRACTCS_PROGSIZE_OFFSET)
 863 /*
 864 * 1: An abstract command is currently being executed.
 865 *
 866 * This bit is set as soon as \Rcommand is written, and is
 867 * not cleared until that command has completed.
 868  */
 869 #define DMI_ABSTRACTCS_BUSY_OFFSET          12
 870 #define DMI_ABSTRACTCS_BUSY_LENGTH          1
 871 #define DMI_ABSTRACTCS_BUSY                 (0x1 << DMI_ABSTRACTCS_BUSY_OFFSET)
 872 /*
 873 * Gets set if an abstract command fails. The bits in this field remain set until
 874 * they are cleared by writing 1 to them. No abstract command is
 875 * started until the value is reset to 0.
 876 *
 877 * 0 (none): No error.
 878 *
 879 * 1 (busy): An abstract command was executing while \Rcommand or one
 880 * of the {\tt data} registers was accessed.
 881 *
 882 * 2 (not supported): The requested command is not supported. A
 883 * command that is not supported while the hart is running may be
 884 * supported when it is halted.
 885 *
 886 * 3 (exception): An exception occurred while executing the command
 887 * (eg. while executing the Program Buffer).
 888 *
 889 * 4 (halt/resume): An abstract command couldn't execute because the
 890 * hart wasn't in the expected state (running/halted).
 891 *
 892 * 7 (other): The command failed for another reason.
 893  */
 894 #define DMI_ABSTRACTCS_CMDERR_OFFSET        8
 895 #define DMI_ABSTRACTCS_CMDERR_LENGTH        3
 896 #define DMI_ABSTRACTCS_CMDERR               (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET)
 897 /*
 898 * Number of {\tt data} registers that are implemented as part of the
 899 * abstract command interface. Valid sizes are 0 - 8.
 900  */
 901 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET     0
 902 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH     5
 903 #define DMI_ABSTRACTCS_DATACOUNT            (0x1f << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
 904 #define DMI_COMMAND                         0x17
 905 /*
 906 * The type determines the overall functionality of this
 907 * abstract command.
 908  */
 909 #define DMI_COMMAND_CMDTYPE_OFFSET          24
 910 #define DMI_COMMAND_CMDTYPE_LENGTH          8
 911 #define DMI_COMMAND_CMDTYPE                 (0xff << DMI_COMMAND_CMDTYPE_OFFSET)
 912 /*
 913 * This field is interpreted in a command-specific manner,
 914 * described for each abstract command.
 915  */
 916 #define DMI_COMMAND_CONTROL_OFFSET          0
 917 #define DMI_COMMAND_CONTROL_LENGTH          24
 918 #define DMI_COMMAND_CONTROL                 (0xffffff << DMI_COMMAND_CONTROL_OFFSET)
 919 #define DMI_ABSTRACTAUTO                    0x18
 920 /*
 921 * When a bit in this field is 1, read or write accesses the corresponding {\tt progbuf} word
 922 * cause the command in \Rcommand to be executed again.
 923  */
 924 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
 925 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
 926 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF    (0xffff << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
 927 /*
 928 * When a bit in this field is 1, read or write accesses the corresponding {\tt data} word
 929 * cause the command in \Rcommand to be executed again.
 930  */
 931 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
 932 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
 933 #define DMI_ABSTRACTAUTO_AUTOEXECDATA       (0xfff << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
 934 #define DMI_CFGSTRADDR0                     0x19
 935 #define DMI_CFGSTRADDR0_ADDR_OFFSET         0
 936 #define DMI_CFGSTRADDR0_ADDR_LENGTH         32
 937 #define DMI_CFGSTRADDR0_ADDR                (0xffffffff << DMI_CFGSTRADDR0_ADDR_OFFSET)
 938 #define DMI_CFGSTRADDR1                     0x1a
 939 #define DMI_CFGSTRADDR2                     0x1b
 940 #define DMI_CFGSTRADDR3                     0x1c
 941 #define DMI_DATA0                           0x04
 942 #define DMI_DATA0_DATA_OFFSET               0
 943 #define DMI_DATA0_DATA_LENGTH               32
 944 #define DMI_DATA0_DATA                      (0xffffffff << DMI_DATA0_DATA_OFFSET)
 945 #define DMI_DATA1                           0x05
 946 #define DMI_DATA2                           0x06
 947 #define DMI_DATA3                           0x07
 948 #define DMI_DATA4                           0x08
 949 #define DMI_DATA5                           0x09
 950 #define DMI_DATA6                           0x0a
 951 #define DMI_DATA7                           0x0b
 952 #define DMI_DATA8                           0x0c
 953 #define DMI_DATA9                           0x0d
 954 #define DMI_DATA10                          0x0e
 955 #define DMI_DATA11                          0x0f
 956 #define DMI_PROGBUF0                        0x20
 957 #define DMI_PROGBUF0_DATA_OFFSET            0
 958 #define DMI_PROGBUF0_DATA_LENGTH            32
 959 #define DMI_PROGBUF0_DATA                   (0xffffffff << DMI_PROGBUF0_DATA_OFFSET)
 960 #define DMI_PROGBUF1                        0x21
 961 #define DMI_PROGBUF2                        0x22
 962 #define DMI_PROGBUF3                        0x23
 963 #define DMI_PROGBUF4                        0x24
 964 #define DMI_PROGBUF5                        0x25
 965 #define DMI_PROGBUF6                        0x26
 966 #define DMI_PROGBUF7                        0x27
 967 #define DMI_PROGBUF8                        0x28
 968 #define DMI_PROGBUF9                        0x29
 969 #define DMI_PROGBUF10                       0x2a
 970 #define DMI_AUTHDATA                        0x30
 971 #define DMI_AUTHDATA_DATA_OFFSET            0
 972 #define DMI_AUTHDATA_DATA_LENGTH            32
 973 #define DMI_AUTHDATA_DATA                   (0xffffffff << DMI_AUTHDATA_DATA_OFFSET)
 974 #define DMI_SERCS                           0x34
 975 /*
 976 * Number of supported serial ports.
 977  */
 978 #define DMI_SERCS_SERIALCOUNT_OFFSET        28
 979 #define DMI_SERCS_SERIALCOUNT_LENGTH        4
 980 #define DMI_SERCS_SERIALCOUNT               (0xf << DMI_SERCS_SERIALCOUNT_OFFSET)
 981 /*
 982 * Select which serial port is accessed by \Rserrx and \Rsertx.
 983  */
 984 #define DMI_SERCS_SERIAL_OFFSET             24
 985 #define DMI_SERCS_SERIAL_LENGTH             3
 986 #define DMI_SERCS_SERIAL                    (0x7 << DMI_SERCS_SERIAL_OFFSET)
 987 #define DMI_SERCS_ERROR7_OFFSET             23
 988 #define DMI_SERCS_ERROR7_LENGTH             1
 989 #define DMI_SERCS_ERROR7                    (0x1 << DMI_SERCS_ERROR7_OFFSET)
 990 #define DMI_SERCS_VALID7_OFFSET             22
 991 #define DMI_SERCS_VALID7_LENGTH             1
 992 #define DMI_SERCS_VALID7                    (0x1 << DMI_SERCS_VALID7_OFFSET)
 993 #define DMI_SERCS_FULL7_OFFSET              21
 994 #define DMI_SERCS_FULL7_LENGTH              1
 995 #define DMI_SERCS_FULL7                     (0x1 << DMI_SERCS_FULL7_OFFSET)
 996 #define DMI_SERCS_ERROR6_OFFSET             20
 997 #define DMI_SERCS_ERROR6_LENGTH             1
 998 #define DMI_SERCS_ERROR6                    (0x1 << DMI_SERCS_ERROR6_OFFSET)
 999 #define DMI_SERCS_VALID6_OFFSET             19
1000 #define DMI_SERCS_VALID6_LENGTH             1
1001 #define DMI_SERCS_VALID6                    (0x1 << DMI_SERCS_VALID6_OFFSET)
1002 #define DMI_SERCS_FULL6_OFFSET              18
1003 #define DMI_SERCS_FULL6_LENGTH              1
1004 #define DMI_SERCS_FULL6                     (0x1 << DMI_SERCS_FULL6_OFFSET)
1005 #define DMI_SERCS_ERROR5_OFFSET             17
1006 #define DMI_SERCS_ERROR5_LENGTH             1
1007 #define DMI_SERCS_ERROR5                    (0x1 << DMI_SERCS_ERROR5_OFFSET)
1008 #define DMI_SERCS_VALID5_OFFSET             16
1009 #define DMI_SERCS_VALID5_LENGTH             1
1010 #define DMI_SERCS_VALID5                    (0x1 << DMI_SERCS_VALID5_OFFSET)
1011 #define DMI_SERCS_FULL5_OFFSET              15
1012 #define DMI_SERCS_FULL5_LENGTH              1
1013 #define DMI_SERCS_FULL5                     (0x1 << DMI_SERCS_FULL5_OFFSET)
1014 #define DMI_SERCS_ERROR4_OFFSET             14
1015 #define DMI_SERCS_ERROR4_LENGTH             1
1016 #define DMI_SERCS_ERROR4                    (0x1 << DMI_SERCS_ERROR4_OFFSET)
1017 #define DMI_SERCS_VALID4_OFFSET             13
1018 #define DMI_SERCS_VALID4_LENGTH             1
1019 #define DMI_SERCS_VALID4                    (0x1 << DMI_SERCS_VALID4_OFFSET)
1020 #define DMI_SERCS_FULL4_OFFSET              12
1021 #define DMI_SERCS_FULL4_LENGTH              1
1022 #define DMI_SERCS_FULL4                     (0x1 << DMI_SERCS_FULL4_OFFSET)
1023 #define DMI_SERCS_ERROR3_OFFSET             11
1024 #define DMI_SERCS_ERROR3_LENGTH             1
1025 #define DMI_SERCS_ERROR3                    (0x1 << DMI_SERCS_ERROR3_OFFSET)
1026 #define DMI_SERCS_VALID3_OFFSET             10
1027 #define DMI_SERCS_VALID3_LENGTH             1
1028 #define DMI_SERCS_VALID3                    (0x1 << DMI_SERCS_VALID3_OFFSET)
1029 #define DMI_SERCS_FULL3_OFFSET              9
1030 #define DMI_SERCS_FULL3_LENGTH              1
1031 #define DMI_SERCS_FULL3                     (0x1 << DMI_SERCS_FULL3_OFFSET)
1032 #define DMI_SERCS_ERROR2_OFFSET             8
1033 #define DMI_SERCS_ERROR2_LENGTH             1
1034 #define DMI_SERCS_ERROR2                    (0x1 << DMI_SERCS_ERROR2_OFFSET)
1035 #define DMI_SERCS_VALID2_OFFSET             7
1036 #define DMI_SERCS_VALID2_LENGTH             1
1037 #define DMI_SERCS_VALID2                    (0x1 << DMI_SERCS_VALID2_OFFSET)
1038 #define DMI_SERCS_FULL2_OFFSET              6
1039 #define DMI_SERCS_FULL2_LENGTH              1
1040 #define DMI_SERCS_FULL2                     (0x1 << DMI_SERCS_FULL2_OFFSET)
1041 #define DMI_SERCS_ERROR1_OFFSET             5
1042 #define DMI_SERCS_ERROR1_LENGTH             1
1043 #define DMI_SERCS_ERROR1                    (0x1 << DMI_SERCS_ERROR1_OFFSET)
1044 #define DMI_SERCS_VALID1_OFFSET             4
1045 #define DMI_SERCS_VALID1_LENGTH             1
1046 #define DMI_SERCS_VALID1                    (0x1 << DMI_SERCS_VALID1_OFFSET)
1047 #define DMI_SERCS_FULL1_OFFSET              3
1048 #define DMI_SERCS_FULL1_LENGTH              1
1049 #define DMI_SERCS_FULL1                     (0x1 << DMI_SERCS_FULL1_OFFSET)
1050 /*
1051 * 1 when the debugger-to-core queue for serial port 0 has
1052 * over or underflowed. This bit will remain set until it is reset by
1053 * writing 1 to this bit.
1054  */
1055 #define DMI_SERCS_ERROR0_OFFSET             2
1056 #define DMI_SERCS_ERROR0_LENGTH             1
1057 #define DMI_SERCS_ERROR0                    (0x1 << DMI_SERCS_ERROR0_OFFSET)
1058 /*
1059 * 1 when the core-to-debugger queue for serial port 0 is not empty.
1060  */
1061 #define DMI_SERCS_VALID0_OFFSET             1
1062 #define DMI_SERCS_VALID0_LENGTH             1
1063 #define DMI_SERCS_VALID0                    (0x1 << DMI_SERCS_VALID0_OFFSET)
1064 /*
1065 * 1 when the debugger-to-core queue for serial port 0 is full.
1066  */
1067 #define DMI_SERCS_FULL0_OFFSET              0
1068 #define DMI_SERCS_FULL0_LENGTH              1
1069 #define DMI_SERCS_FULL0                     (0x1 << DMI_SERCS_FULL0_OFFSET)
1070 #define DMI_SERTX                           0x35
1071 #define DMI_SERTX_DATA_OFFSET               0
1072 #define DMI_SERTX_DATA_LENGTH               32
1073 #define DMI_SERTX_DATA                      (0xffffffff << DMI_SERTX_DATA_OFFSET)
1074 #define DMI_SERRX                           0x36
1075 #define DMI_SERRX_DATA_OFFSET               0
1076 #define DMI_SERRX_DATA_LENGTH               32
1077 #define DMI_SERRX_DATA                      (0xffffffff << DMI_SERRX_DATA_OFFSET)
1078 #define DMI_SBCS                            0x38
1079 /*
1080 * When a 1 is written here, triggers a read at the address in {\tt
1081 * sbaddress} using the access size set by \Fsbaccess.
1082  */
1083 #define DMI_SBCS_SBSINGLEREAD_OFFSET        20
1084 #define DMI_SBCS_SBSINGLEREAD_LENGTH        1
1085 #define DMI_SBCS_SBSINGLEREAD               (0x1 << DMI_SBCS_SBSINGLEREAD_OFFSET)
1086 /*
1087 * Select the access size to use for system bus accesses triggered by
1088 * writes to the {\tt sbaddress} registers or \Rsbdatazero.
1089 *
1090 * 0: 8-bit
1091 *
1092 * 1: 16-bit
1093 *
1094 * 2: 32-bit
1095 *
1096 * 3: 64-bit
1097 *
1098 * 4: 128-bit
1099 *
1100 * If an unsupported system bus access size is written here,
1101 * the DM may not perform the access, or may perform the access
1102 * with any access size.
1103  */
1104 #define DMI_SBCS_SBACCESS_OFFSET            17
1105 #define DMI_SBCS_SBACCESS_LENGTH            3
1106 #define DMI_SBCS_SBACCESS                   (0x7 << DMI_SBCS_SBACCESS_OFFSET)
1107 /*
1108 * When 1, the internal address value (used by the system bus master)
1109 * is incremented by the access size (in bytes) selected in \Fsbaccess
1110 * after every system bus access.
1111  */
1112 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET     16
1113 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH     1
1114 #define DMI_SBCS_SBAUTOINCREMENT            (0x1 << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
1115 /*
1116 * When 1, every read from \Rsbdatazero automatically triggers a system
1117 * bus read at the new address.
1118  */
1119 #define DMI_SBCS_SBAUTOREAD_OFFSET          15
1120 #define DMI_SBCS_SBAUTOREAD_LENGTH          1
1121 #define DMI_SBCS_SBAUTOREAD                 (0x1 << DMI_SBCS_SBAUTOREAD_OFFSET)
1122 /*
1123 * When the debug module's system bus
1124 * master causes a bus error, this field gets set. The bits in this
1125 * field remain set until they are cleared by writing 1 to them.
1126 * While this field is non-zero, no more system bus accesses can be
1127 * initiated by the debug module.
1128 *
1129 * 0: There was no bus error.
1130 *
1131 * 1: There was a timeout.
1132 *
1133 * 2: A bad address was accessed.
1134 *
1135 * 3: There was some other error (eg. alignment).
1136 *
1137 * 4: The system bus master was busy when a one of the
1138 * {\tt sbaddress} or {\tt sbdata} registers was written,
1139 * or the {\tt sbdata} register was read when it had
1140 * stale data.
1141  */
1142 #define DMI_SBCS_SBERROR_OFFSET             12
1143 #define DMI_SBCS_SBERROR_LENGTH             3
1144 #define DMI_SBCS_SBERROR                    (0x7 << DMI_SBCS_SBERROR_OFFSET)
1145 /*
1146 * Width of system bus addresses in bits. (0 indicates there is no bus
1147 * access support.)
1148  */
1149 #define DMI_SBCS_SBASIZE_OFFSET             5
1150 #define DMI_SBCS_SBASIZE_LENGTH             7
1151 #define DMI_SBCS_SBASIZE                    (0x7f << DMI_SBCS_SBASIZE_OFFSET)
1152 /*
1153 * 1 when 128-bit system bus accesses are supported.
1154  */
1155 #define DMI_SBCS_SBACCESS128_OFFSET         4
1156 #define DMI_SBCS_SBACCESS128_LENGTH         1
1157 #define DMI_SBCS_SBACCESS128                (0x1 << DMI_SBCS_SBACCESS128_OFFSET)
1158 /*
1159 * 1 when 64-bit system bus accesses are supported.
1160  */
1161 #define DMI_SBCS_SBACCESS64_OFFSET          3
1162 #define DMI_SBCS_SBACCESS64_LENGTH          1
1163 #define DMI_SBCS_SBACCESS64                 (0x1 << DMI_SBCS_SBACCESS64_OFFSET)
1164 /*
1165 * 1 when 32-bit system bus accesses are supported.
1166  */
1167 #define DMI_SBCS_SBACCESS32_OFFSET          2
1168 #define DMI_SBCS_SBACCESS32_LENGTH          1
1169 #define DMI_SBCS_SBACCESS32                 (0x1 << DMI_SBCS_SBACCESS32_OFFSET)
1170 /*
1171 * 1 when 16-bit system bus accesses are supported.
1172  */
1173 #define DMI_SBCS_SBACCESS16_OFFSET          1
1174 #define DMI_SBCS_SBACCESS16_LENGTH          1
1175 #define DMI_SBCS_SBACCESS16                 (0x1 << DMI_SBCS_SBACCESS16_OFFSET)
1176 /*
1177 * 1 when 8-bit system bus accesses are supported.
1178  */
1179 #define DMI_SBCS_SBACCESS8_OFFSET           0
1180 #define DMI_SBCS_SBACCESS8_LENGTH           1
1181 #define DMI_SBCS_SBACCESS8                  (0x1 << DMI_SBCS_SBACCESS8_OFFSET)
1182 #define DMI_SBADDRESS0                      0x39
1183 /*
1184 * Accesses bits 31:0 of the internal address.
1185  */
1186 #define DMI_SBADDRESS0_ADDRESS_OFFSET       0
1187 #define DMI_SBADDRESS0_ADDRESS_LENGTH       32
1188 #define DMI_SBADDRESS0_ADDRESS              (0xffffffff << DMI_SBADDRESS0_ADDRESS_OFFSET)
1189 #define DMI_SBADDRESS1                      0x3a
1190 /*
1191 * Accesses bits 63:32 of the internal address (if the system address
1192 * bus is that wide).
1193  */
1194 #define DMI_SBADDRESS1_ADDRESS_OFFSET       0
1195 #define DMI_SBADDRESS1_ADDRESS_LENGTH       32
1196 #define DMI_SBADDRESS1_ADDRESS              (0xffffffff << DMI_SBADDRESS1_ADDRESS_OFFSET)
1197 #define DMI_SBADDRESS2                      0x3b
1198 /*
1199 * Accesses bits 95:64 of the internal address (if the system address
1200 * bus is that wide).
1201  */
1202 #define DMI_SBADDRESS2_ADDRESS_OFFSET       0
1203 #define DMI_SBADDRESS2_ADDRESS_LENGTH       32
1204 #define DMI_SBADDRESS2_ADDRESS              (0xffffffff << DMI_SBADDRESS2_ADDRESS_OFFSET)
1205 #define DMI_SBDATA0                         0x3c
1206 /*
1207 * Accesses bits 31:0 of the internal data.
1208  */
1209 #define DMI_SBDATA0_DATA_OFFSET             0
1210 #define DMI_SBDATA0_DATA_LENGTH             32
1211 #define DMI_SBDATA0_DATA                    (0xffffffff << DMI_SBDATA0_DATA_OFFSET)
1212 #define DMI_SBDATA1                         0x3d
1213 /*
1214 * Accesses bits 63:32 of the internal data (if the system bus is
1215 * that wide).
1216  */
1217 #define DMI_SBDATA1_DATA_OFFSET             0
1218 #define DMI_SBDATA1_DATA_LENGTH             32
1219 #define DMI_SBDATA1_DATA                    (0xffffffff << DMI_SBDATA1_DATA_OFFSET)
1220 #define DMI_SBDATA2                         0x3e
1221 /*
1222 * Accesses bits 95:64 of the internal data (if the system bus is
1223 * that wide).
1224  */
1225 #define DMI_SBDATA2_DATA_OFFSET             0
1226 #define DMI_SBDATA2_DATA_LENGTH             32
1227 #define DMI_SBDATA2_DATA                    (0xffffffff << DMI_SBDATA2_DATA_OFFSET)
1228 #define DMI_SBDATA3                         0x3f
1229 /*
1230 * Accesses bits 127:96 of the internal data (if the system bus is
1231 * that wide).
1232  */
1233 #define DMI_SBDATA3_DATA_OFFSET             0
1234 #define DMI_SBDATA3_DATA_LENGTH             32
1235 #define DMI_SBDATA3_DATA                    (0xffffffff << DMI_SBDATA3_DATA_OFFSET)
1236 #define SERINFO                             0x280
1237 /*
1238 * Like \Fserialzero.
1239  */
1240 #define SERINFO_SERIAL7_OFFSET              7
1241 #define SERINFO_SERIAL7_LENGTH              1
1242 #define SERINFO_SERIAL7                     (0x1 << SERINFO_SERIAL7_OFFSET)
1243 /*
1244 * Like \Fserialzero.
1245  */
1246 #define SERINFO_SERIAL6_OFFSET              6
1247 #define SERINFO_SERIAL6_LENGTH              1
1248 #define SERINFO_SERIAL6                     (0x1 << SERINFO_SERIAL6_OFFSET)
1249 /*
1250 * Like \Fserialzero.
1251  */
1252 #define SERINFO_SERIAL5_OFFSET              5
1253 #define SERINFO_SERIAL5_LENGTH              1
1254 #define SERINFO_SERIAL5                     (0x1 << SERINFO_SERIAL5_OFFSET)
1255 /*
1256 * Like \Fserialzero.
1257  */
1258 #define SERINFO_SERIAL4_OFFSET              4
1259 #define SERINFO_SERIAL4_LENGTH              1
1260 #define SERINFO_SERIAL4                     (0x1 << SERINFO_SERIAL4_OFFSET)
1261 /*
1262 * Like \Fserialzero.
1263  */
1264 #define SERINFO_SERIAL3_OFFSET              3
1265 #define SERINFO_SERIAL3_LENGTH              1
1266 #define SERINFO_SERIAL3                     (0x1 << SERINFO_SERIAL3_OFFSET)
1267 /*
1268 * Like \Fserialzero.
1269  */
1270 #define SERINFO_SERIAL2_OFFSET              2
1271 #define SERINFO_SERIAL2_LENGTH              1
1272 #define SERINFO_SERIAL2                     (0x1 << SERINFO_SERIAL2_OFFSET)
1273 /*
1274 * Like \Fserialzero.
1275  */
1276 #define SERINFO_SERIAL1_OFFSET              1
1277 #define SERINFO_SERIAL1_LENGTH              1
1278 #define SERINFO_SERIAL1                     (0x1 << SERINFO_SERIAL1_OFFSET)
1279 /*
1280 * 1 means serial interface 0 is supported.
1281  */
1282 #define SERINFO_SERIAL0_OFFSET              0
1283 #define SERINFO_SERIAL0_LENGTH              1
1284 #define SERINFO_SERIAL0                     (0x1 << SERINFO_SERIAL0_OFFSET)
1285 #define SERSEND0                            0x200
1286 #define SERRECV0                            0x204
1287 #define SERSTAT0                            0x208
1288 /*
1289 * Send ready. 1 when the core-to-debugger queue is not full. 0
1290 * otherwise.
1291  */
1292 #define SERSTAT0_SENDR_OFFSET               1
1293 #define SERSTAT0_SENDR_LENGTH               1
1294 #define SERSTAT0_SENDR                      (0x1 << SERSTAT0_SENDR_OFFSET)
1295 /*
1296 * Receive ready. 1 when the debugger-to-core queue is not empty. 0
1297 * otherwise.
1298  */
1299 #define SERSTAT0_RECVR_OFFSET               0
1300 #define SERSTAT0_RECVR_LENGTH               1
1301 #define SERSTAT0_RECVR                      (0x1 << SERSTAT0_RECVR_OFFSET)
1302 #define SERSEND1                            0x210
1303 #define SERRECV1                            0x214
1304 #define SERSTAT1                            0x218
1305 #define SERSEND2                            0x220
1306 #define SERRECV2                            0x224
1307 #define SERSTAT2                            0x228
1308 #define SERSEND3                            0x230
1309 #define SERRECV3                            0x234
1310 #define SERSTAT3                            0x238
1311 #define SERSEND4                            0x240
1312 #define SERRECV4                            0x244
1313 #define SERSTAT4                            0x248
1314 #define SERSEND5                            0x250
1315 #define SERRECV5                            0x254
1316 #define SERSTAT5                            0x258
1317 #define SERSEND6                            0x260
1318 #define SERRECV6                            0x264
1319 #define SERSTAT6                            0x268
1320 #define SERSEND7                            0x274
1321 #define SERRECV7                            0x278
1322 #define SERSTAT7                            0x27c
1323 #define TRACE                               0x728
1324 /*
1325 * 1 if the trace buffer has wrapped since the last time \Fdiscard was
1326 * written. 0 otherwise.
1327  */
1328 #define TRACE_WRAPPED_OFFSET                24
1329 #define TRACE_WRAPPED_LENGTH                1
1330 #define TRACE_WRAPPED                       (0x1 << TRACE_WRAPPED_OFFSET)
1331 /*
1332 * Emit Timestamp trace sequences.
1333  */
1334 #define TRACE_EMITTIMESTAMP_OFFSET          23
1335 #define TRACE_EMITTIMESTAMP_LENGTH          1
1336 #define TRACE_EMITTIMESTAMP                 (0x1 << TRACE_EMITTIMESTAMP_OFFSET)
1337 /*
1338 * Emit Store Data trace sequences.
1339  */
1340 #define TRACE_EMITSTOREDATA_OFFSET          22
1341 #define TRACE_EMITSTOREDATA_LENGTH          1
1342 #define TRACE_EMITSTOREDATA                 (0x1 << TRACE_EMITSTOREDATA_OFFSET)
1343 /*
1344 * Emit Load Data trace sequences.
1345  */
1346 #define TRACE_EMITLOADDATA_OFFSET           21
1347 #define TRACE_EMITLOADDATA_LENGTH           1
1348 #define TRACE_EMITLOADDATA                  (0x1 << TRACE_EMITLOADDATA_OFFSET)
1349 /*
1350 * Emit Store Address trace sequences.
1351  */
1352 #define TRACE_EMITSTOREADDR_OFFSET          20
1353 #define TRACE_EMITSTOREADDR_LENGTH          1
1354 #define TRACE_EMITSTOREADDR                 (0x1 << TRACE_EMITSTOREADDR_OFFSET)
1355 /*
1356 * Emit Load Address trace sequences.
1357  */
1358 #define TRACE_EMITLOADADDR_OFFSET           19
1359 #define TRACE_EMITLOADADDR_LENGTH           1
1360 #define TRACE_EMITLOADADDR                  (0x1 << TRACE_EMITLOADADDR_OFFSET)
1361 /*
1362 * Emit Privilege Level trace sequences.
1363  */
1364 #define TRACE_EMITPRIV_OFFSET               18
1365 #define TRACE_EMITPRIV_LENGTH               1
1366 #define TRACE_EMITPRIV                      (0x1 << TRACE_EMITPRIV_OFFSET)
1367 /*
1368 * Emit Branch Taken and Branch Not Taken trace sequences.
1369  */
1370 #define TRACE_EMITBRANCH_OFFSET             17
1371 #define TRACE_EMITBRANCH_LENGTH             1
1372 #define TRACE_EMITBRANCH                    (0x1 << TRACE_EMITBRANCH_OFFSET)
1373 /*
1374 * Emit PC trace sequences.
1375  */
1376 #define TRACE_EMITPC_OFFSET                 16
1377 #define TRACE_EMITPC_LENGTH                 1
1378 #define TRACE_EMITPC                        (0x1 << TRACE_EMITPC_OFFSET)
1379 /*
1380 * Determine what happens when the trace buffer is full.  0 means wrap
1381 * and overwrite. 1 means turn off trace until \Fdiscard is written as 1.
1382 * 2 means cause a trace full exception. 3 is reserved for future use.
1383  */
1384 #define TRACE_FULLACTION_OFFSET             8
1385 #define TRACE_FULLACTION_LENGTH             2
1386 #define TRACE_FULLACTION                    (0x3 << TRACE_FULLACTION_OFFSET)
1387 /*
1388 * 0: Trace to a dedicated on-core RAM (which is not further defined in
1389 * this spec).
1390 *
1391 * 1: Trace to RAM on the system bus.
1392 *
1393 * 2: Send trace data to a dedicated off-chip interface (which is not
1394 * defined in this spec). This does not affect execution speed.
1395 *
1396 * 3: Reserved for future use.
1397 *
1398 * Options 0 and 1 slow down execution (eg. because of system bus
1399 * contention).
1400  */
1401 #define TRACE_DESTINATION_OFFSET            4
1402 #define TRACE_DESTINATION_LENGTH            2
1403 #define TRACE_DESTINATION                   (0x3 << TRACE_DESTINATION_OFFSET)
1404 /*
1405 * When 1, the trace logic may stall processor execution to ensure it
1406 * can emit all the trace sequences required. When 0 individual trace
1407 * sequences may be dropped.
1408  */
1409 #define TRACE_STALL_OFFSET                  2
1410 #define TRACE_STALL_LENGTH                  1
1411 #define TRACE_STALL                         (0x1 << TRACE_STALL_OFFSET)
1412 /*
1413 * Writing 1 to this bit tells the trace logic that any trace
1414 * collected is no longer required. When tracing to RAM, it resets the
1415 * trace write pointer to the start of the memory, as well as
1416 * \Fwrapped.
1417  */
1418 #define TRACE_DISCARD_OFFSET                1
1419 #define TRACE_DISCARD_LENGTH                1
1420 #define TRACE_DISCARD                       (0x1 << TRACE_DISCARD_OFFSET)
1421 #define TRACE_SUPPORTED_OFFSET              0
1422 #define TRACE_SUPPORTED_LENGTH              1
1423 #define TRACE_SUPPORTED                     (0x1 << TRACE_SUPPORTED_OFFSET)
1424 #define TBUFSTART                           0x729
1425 #define TBUFEND                             0x72a
1426 #define TBUFWRITE                           0x72b
1427 #define SHORTNAME                           0x123
1428 /*
1429 * Description of what this field is used for.
1430  */
1431 #define SHORTNAME_FIELD_OFFSET              0
1432 #define SHORTNAME_FIELD_LENGTH              8
1433 #define SHORTNAME_FIELD                     (0xff << SHORTNAME_FIELD_OFFSET)
1434 #define AC_ACCESS_REGISTER                  None
1435 /*
1436 * This is 0 to indicate Access Register Command.
1437  */
1438 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET   24
1439 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH   8
1440 #define AC_ACCESS_REGISTER_CMDTYPE          (0xff << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
1441 /*
1442 * 2: Access the lowest 32 bits of the register.
1443 *
1444 * 3: Access the lowest 64 bits of the register.
1445 *
1446 * 4: Access the lowest 128 bits of the register.
1447 *
1448 * If \Fsize specifies a size larger than the register's actual size,
1449 * then the access must fail. If a register is accessible, then reads of \Fsize
1450 * less than or equal to the register's actual size must be supported.
1451  */
1452 #define AC_ACCESS_REGISTER_SIZE_OFFSET      20
1453 #define AC_ACCESS_REGISTER_SIZE_LENGTH      3
1454 #define AC_ACCESS_REGISTER_SIZE             (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET)
1455 /*
1456 * When 1, execute the program in the Program Buffer exactly once
1457 * before performing the transfer.
1458 * \textbf{WARNING: preexec is considered for removal.}
1459  */
1460 #define AC_ACCESS_REGISTER_PREEXEC_OFFSET   19
1461 #define AC_ACCESS_REGISTER_PREEXEC_LENGTH   1
1462 #define AC_ACCESS_REGISTER_PREEXEC          (0x1 << AC_ACCESS_REGISTER_PREEXEC_OFFSET)
1463 /*
1464 * When 1, execute the program in the Program Buffer exactly once
1465 * after performing the transfer, if any.
1466  */
1467 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET  18
1468 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH  1
1469 #define AC_ACCESS_REGISTER_POSTEXEC         (0x1 << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1470 /*
1471 * 0: Don't do the operation specified by \Fwrite.
1472 *
1473 * 1: Do the operation specified by \Fwrite.
1474  */
1475 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET  17
1476 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH  1
1477 #define AC_ACCESS_REGISTER_TRANSFER         (0x1 << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
1478 /*
1479 * When \Ftransfer is set:
1480 * 0: Copy data from the specified register into {\tt arg0} portion
1481 * of {\tt data}.
1482 *
1483 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1484 * specified register.
1485  */
1486 #define AC_ACCESS_REGISTER_WRITE_OFFSET     16
1487 #define AC_ACCESS_REGISTER_WRITE_LENGTH     1
1488 #define AC_ACCESS_REGISTER_WRITE            (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET)
1489 /*
1490 * Number of the register to access, as described in Table~\ref{tab:regno}.
1491  */
1492 #define AC_ACCESS_REGISTER_REGNO_OFFSET     0
1493 #define AC_ACCESS_REGISTER_REGNO_LENGTH     16
1494 #define AC_ACCESS_REGISTER_REGNO            (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET)
1495 #define AC_QUICK_ACCESS                     None
1496 /*
1497 * This is 1 to indicate Quick Access command.
1498  */
1499 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET      24
1500 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH      8
1501 #define AC_QUICK_ACCESS_CMDTYPE             (0xff << AC_QUICK_ACCESS_CMDTYPE_OFFSET)