riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "debug_defines.h"
   5 #include "opcodes.h"
   6 #include "mmu.h"
   7
   8 #include "debug_rom/debug_rom.h"
   9 #include "debug_rom/debug_rom_defines.h"
  10
  11 #if 1
  12 #  define D(x) x
  13 #else
  14 #  define D(x)
  15 #endif
  16
  17 ///////////////////////// debug_module_t
  18
  19 debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) :
  20   progbufsize(progbufsize),
  21   program_buffer_bytes(4 + 4*progbufsize),
  22   max_bus_master_bits(max_bus_master_bits),
  23   debug_progbuf_start(debug_data_start - program_buffer_bytes),
  24   debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
  25   sim(sim)
  26 {
  27   D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
  28   D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));
  29   D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start));
  30
  31   program_buffer = new uint8_t[program_buffer_bytes];
  32
  33   memset(halted, 0, sizeof(halted));
  34   memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
  35   memset(resumeack, 0, sizeof(resumeack));
  36   memset(program_buffer, 0, program_buffer_bytes);
  37   program_buffer[4*progbufsize] = ebreak();
  38   program_buffer[4*progbufsize+1] = ebreak() >> 8;
  39   program_buffer[4*progbufsize+2] = ebreak() >> 16;
  40   program_buffer[4*progbufsize+3] = ebreak() >> 24;
  41   memset(dmdata, 0, sizeof(dmdata));
  42
  43   write32(debug_rom_whereto, 0,
  44           jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO));
  45
  46   memset(debug_abstract, 0, sizeof(debug_abstract));
  47
  48   reset();
  49 }
  50
  51 debug_module_t::~debug_module_t()
  52 {
  53   delete[] program_buffer;
  54 }
  55
  56 void debug_module_t::reset()
  57 {
  58   for (unsigned i = 0; i < sim->nprocs(); i++) {
  59     processor_t *proc = sim->get_core(i);
  60     if (proc)
  61       proc->halt_request = false;
  62   }
  63
  64   dmcontrol = {0};
  65
  66   dmstatus = {0};
  67   dmstatus.impebreak = true;
  68   dmstatus.authenticated = 1;
  69   dmstatus.version = 2;
  70
  71   abstractcs = {0};
  72   abstractcs.datacount = sizeof(dmdata) / 4;
  73   abstractcs.progbufsize = progbufsize;
  74
  75   abstractauto = {0};
  76
  77   sbcs = {0};
  78   if (max_bus_master_bits > 0) {
  79     sbcs.version = 1;
  80     sbcs.asize = sizeof(reg_t) * 8;
  81   }
  82   if (max_bus_master_bits >= 64)
  83     sbcs.access64 = true;
  84   if (max_bus_master_bits >= 32)
  85     sbcs.access32 = true;
  86   if (max_bus_master_bits >= 16)
  87     sbcs.access16 = true;
  88   if (max_bus_master_bits >= 8)
  89     sbcs.access8 = true;
  90 }
  91
  92 void debug_module_t::add_device(bus_t *bus) {
  93   bus->add_device(DEBUG_START, this);
  94 }
  95
  96 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
  97 {
  98   addr = DEBUG_START + addr;
  99
 100   if (addr >= DEBUG_ROM_ENTRY &&
 101       (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) {
 102     memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len);
 103     return true;
 104   }
 105
 106   if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) {
 107     memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len);
 108     return true;
 109   }
 110
 111   if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) {
 112     memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len);
 113     return true;
 114   }
 115
 116   if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) {
 117     memcpy(bytes, debug_abstract + addr - debug_abstract_start, len);
 118     return true;
 119   }
 120
 121   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 122     memcpy(bytes, dmdata + addr - debug_data_start, len);
 123     return true;
 124   }
 125
 126   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) {
 127     memcpy(bytes, program_buffer + addr - debug_progbuf_start, len);
 128     return true;
 129   }
 130
 131   fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
 132           PRIx64 "\n", len, addr);
 133
 134   return false;
 135 }
 136
 137 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 138 {
 139   D(
 140       switch (len) {
 141         case 4:
 142           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); "
 143               "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes,
 144               dmcontrol.hartsel);
 145           break;
 146         default:
 147           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); "
 148               "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel);
 149           break;
 150       }
 151    );
 152
 153   uint8_t id_bytes[4];
 154   uint32_t id = 0;
 155   if (len == 4) {
 156     memcpy(id_bytes, bytes, 4);
 157     id = read32(id_bytes, 0);
 158   }
 159
 160   addr = DEBUG_START + addr;
 161
 162   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 163     memcpy(dmdata + addr - debug_data_start, bytes, len);
 164     return true;
 165   }
 166
 167   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) {
 168     memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
 169
 170     return true;
 171   }
 172
 173   if (addr == DEBUG_ROM_HALTED) {
 174     assert (len == 4);
 175     halted[id] = true;
 176     if (dmcontrol.hartsel == id) {
 177         if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){
 178           if (dmcontrol.hartsel == id) {
 179               abstractcs.busy = false;
 180           }
 181         }
 182     }
 183     return true;
 184   }
 185
 186   if (addr == DEBUG_ROM_GOING) {
 187     debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO);
 188     return true;
 189   }
 190
 191   if (addr == DEBUG_ROM_RESUMING) {
 192     assert (len == 4);
 193     halted[id] = false;
 194     resumeack[id] = true;
 195     debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME);
 196     return true;
 197   }
 198
 199   if (addr == DEBUG_ROM_EXCEPTION) {
 200     if (abstractcs.cmderr == CMDERR_NONE) {
 201       abstractcs.cmderr = CMDERR_EXCEPTION;
 202     }
 203     return true;
 204   }
 205
 206   fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
 207           PRIx64 "\n", len, addr);
 208   return false;
 209 }
 210
 211 void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value)
 212 {
 213   uint8_t* base = memory + index * 4;
 214   base[0] = value & 0xff;
 215   base[1] = (value >> 8) & 0xff;
 216   base[2] = (value >> 16) & 0xff;
 217   base[3] = (value >> 24) & 0xff;
 218 }
 219
 220 uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index)
 221 {
 222   uint8_t* base = memory + index * 4;
 223   uint32_t value = ((uint32_t) base[0]) |
 224     (((uint32_t) base[1]) << 8) |
 225     (((uint32_t) base[2]) << 16) |
 226     (((uint32_t) base[3]) << 24);
 227   return value;
 228 }
 229
 230 processor_t *debug_module_t::current_proc() const
 231 {
 232   processor_t *proc = NULL;
 233   try {
 234     proc = sim->get_core(dmcontrol.hartsel);
 235   } catch (const std::out_of_range&) {
 236   }
 237   return proc;
 238 }
 239
 240 unsigned debug_module_t::sb_access_bits()
 241 {
 242   return 8 << sbcs.sbaccess;
 243 }
 244
 245 void debug_module_t::sb_autoincrement()
 246 {
 247   if (!sbcs.autoincrement || !max_bus_master_bits)
 248     return;
 249
 250   uint64_t value = sbaddress[0] + sb_access_bits() / 8;
 251   sbaddress[0] = value;
 252   uint32_t carry = value >> 32;
 253
 254   value = sbaddress[1] + carry;
 255   sbaddress[1] = value;
 256   carry = value >> 32;
 257
 258   value = sbaddress[2] + carry;
 259   sbaddress[2] = value;
 260   carry = value >> 32;
 261
 262   sbaddress[3] += carry;
 263 }
 264
 265 void debug_module_t::sb_read()
 266 {
 267   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
 268   try {
 269     if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
 270       sbdata[0] = sim->debug_mmu->load_uint8(address);
 271     } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
 272       sbdata[0] = sim->debug_mmu->load_uint16(address);
 273     } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
 274       sbdata[0] = sim->debug_mmu->load_uint32(address);
 275     } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
 276       uint64_t value = sim->debug_mmu->load_uint32(address);
 277       sbdata[0] = value;
 278       sbdata[1] = value >> 32;
 279     } else {
 280       sbcs.error = 3;
 281     }
 282   } catch (trap_load_access_fault& t) {
 283     sbcs.error = 2;
 284   }
 285 }
 286
 287 void debug_module_t::sb_write()
 288 {
 289   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
 290   D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
 291   if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
 292     sim->debug_mmu->store_uint8(address, sbdata[0]);
 293   } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
 294     sim->debug_mmu->store_uint16(address, sbdata[0]);
 295   } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
 296     sim->debug_mmu->store_uint32(address, sbdata[0]);
 297   } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
 298     sim->debug_mmu->store_uint64(address,
 299         (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
 300   } else {
 301     sbcs.error = 3;
 302   }
 303 }
 304
 305 bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 306 {
 307   uint32_t result = 0;
 308   D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
 309   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 310     unsigned i = address - DMI_DATA0;
 311     result = read32(dmdata, i);
 312     if (abstractcs.busy) {
 313       result = -1;
 314       fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 315     }
 316
 317     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 318       abstractcs.cmderr = CMDERR_BUSY;
 319     }
 320
 321     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 322       perform_abstract_command();
 323     }
 324   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) {
 325     unsigned i = address - DMI_PROGBUF0;
 326     result = read32(program_buffer, i);
 327     if (abstractcs.busy) {
 328       result = -1;
 329       fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 330     }
 331     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 332       perform_abstract_command();
 333     }
 334
 335   } else {
 336     switch (address) {
 337       case DMI_DMCONTROL:
 338         {
 339           processor_t *proc = current_proc();
 340           if (proc)
 341             dmcontrol.haltreq = proc->halt_request;
 342
 343           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
 344           result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
 345           result = set_field(result, ((1L<<hartsellen)-1) <<
 346               DMI_DMCONTROL_HARTSEL_OFFSET, dmcontrol.hartsel);
 347           result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
 348           result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
 349           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
 350         }
 351         break;
 352       case DMI_DMSTATUS:
 353         {
 354           processor_t *proc = current_proc();
 355
 356           dmstatus.allnonexistant = false;
 357           dmstatus.allunavail = false;
 358           dmstatus.allrunning = false;
 359           dmstatus.allhalted = false;
 360           dmstatus.allresumeack = false;
 361           if (proc) {
 362             if (halted[dmcontrol.hartsel]) {
 363               dmstatus.allhalted = true;
 364             } else {
 365               dmstatus.allrunning = true;
 366             }
 367           } else {
 368             dmstatus.allnonexistant = true;
 369           }
 370           dmstatus.anynonexistant = dmstatus.allnonexistant;
 371           dmstatus.anyunavail = dmstatus.allunavail;
 372           dmstatus.anyrunning = dmstatus.allrunning;
 373           dmstatus.anyhalted = dmstatus.allhalted;
 374           if (proc) {
 375             if (resumeack[dmcontrol.hartsel]) {
 376               dmstatus.allresumeack = true;
 377             } else {
 378               dmstatus.allresumeack = false;
 379             }
 380           } else {
 381             dmstatus.allresumeack = false;
 382           }
 383
 384           result = set_field(result, DMI_DMSTATUS_IMPEBREAK,
 385               dmstatus.impebreak);
 386           result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
 387           result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
 388           result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
 389           result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted);
 390           result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack);
 391           result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant);
 392           result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail);
 393           result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning);
 394           result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted);
 395           result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack);
 396           result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated);
 397           result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy);
 398           result = set_field(result, DMI_DMSTATUS_VERSION, dmstatus.version);
 399         }
 400         break;
 401       case DMI_ABSTRACTCS:
 402         result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr);
 403         result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy);
 404         result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount);
 405         result = set_field(result, DMI_ABSTRACTCS_PROGBUFSIZE,
 406             abstractcs.progbufsize);
 407         break;
 408       case DMI_ABSTRACTAUTO:
 409         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf);
 410         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata);
 411         break;
 412       case DMI_COMMAND:
 413         result = 0;
 414         break;
 415       case DMI_HARTINFO:
 416         result = set_field(result, DMI_HARTINFO_NSCRATCH, 1);
 417         result = set_field(result, DMI_HARTINFO_DATAACCESS, 1);
 418         result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount);
 419         result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start);
 420         break;
 421       case DMI_SBCS:
 422         result = set_field(result, DMI_SBCS_SBVERSION, sbcs.version);
 423         result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr);
 424         result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess);
 425         result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement);
 426         result = set_field(result, DMI_SBCS_SBREADONDATA, sbcs.readondata);
 427         result = set_field(result, DMI_SBCS_SBERROR, sbcs.error);
 428         result = set_field(result, DMI_SBCS_SBASIZE, sbcs.asize);
 429         result = set_field(result, DMI_SBCS_SBACCESS128, sbcs.access128);
 430         result = set_field(result, DMI_SBCS_SBACCESS64, sbcs.access64);
 431         result = set_field(result, DMI_SBCS_SBACCESS32, sbcs.access32);
 432         result = set_field(result, DMI_SBCS_SBACCESS16, sbcs.access16);
 433         result = set_field(result, DMI_SBCS_SBACCESS8, sbcs.access8);
 434         break;
 435       case DMI_SBADDRESS0:
 436         result = sbaddress[0];
 437         break;
 438       case DMI_SBADDRESS1:
 439         result = sbaddress[1];
 440         break;
 441       case DMI_SBADDRESS2:
 442         result = sbaddress[2];
 443         break;
 444       case DMI_SBADDRESS3:
 445         result = sbaddress[3];
 446         break;
 447       case DMI_SBDATA0:
 448         result = sbdata[0];
 449         if (sbcs.error == 0) {
 450           sb_autoincrement();
 451           if (sbcs.readondata) {
 452             sb_read();
 453           }
 454         }
 455         break;
 456       case DMI_SBDATA1:
 457         result = sbdata[1];
 458         break;
 459       case DMI_SBDATA2:
 460         result = sbdata[2];
 461         break;
 462       case DMI_SBDATA3:
 463         result = sbdata[3];
 464         break;
 465       default:
 466         result = 0;
 467         D(fprintf(stderr, "Unexpected. Returning Error."));
 468         return false;
 469     }
 470   }
 471   D(fprintf(stderr, "0x%x\n", result));
 472   *value = result;
 473   return true;
 474 }
 475
 476 bool debug_module_t::perform_abstract_command()
 477 {
 478   if (abstractcs.cmderr != CMDERR_NONE)
 479     return true;
 480   if (abstractcs.busy) {
 481     abstractcs.cmderr = CMDERR_BUSY;
 482     return true;
 483   }
 484
 485   D(fprintf(stderr, ">>> perform_abstract_command(0x%x)\n", command));
 486
 487   if ((command >> 24) == 0) {
 488     // register access
 489     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
 490     bool write = get_field(command, AC_ACCESS_REGISTER_WRITE);
 491     unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO);
 492
 493     if (!halted[dmcontrol.hartsel]) {
 494       abstractcs.cmderr = CMDERR_HALTRESUME;
 495       return true;
 496     }
 497
 498     if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
 499
 500       if (regno >= 0x1000 && regno < 0x1020) {
 501         unsigned regnum = regno - 0x1000;
 502
 503         switch (size) {
 504           case 2:
 505             if (write)
 506               write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
 507             else
 508               write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
 509             break;
 510           case 3:
 511             if (write)
 512               write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
 513             else
 514               write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
 515             break;
 516           default:
 517             abstractcs.cmderr = CMDERR_NOTSUP;
 518             return true;
 519         }
 520
 521       } else {
 522         abstractcs.cmderr = CMDERR_NOTSUP;
 523         return true;
 524       }
 525
 526       if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
 527         D(fprintf(stderr, ">>> post-exec!\n"));
 528         write32(debug_abstract, 1,
 529             jal(ZERO, debug_progbuf_start - debug_abstract_start - 4));
 530       } else {
 531         write32(debug_abstract, 1, ebreak());
 532       }
 533     }
 534
 535     debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
 536
 537     abstractcs.busy = true;
 538   } else {
 539     abstractcs.cmderr = CMDERR_NOTSUP;
 540   }
 541   return true;
 542 }
 543
 544 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 545 {
 546   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
 547   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 548     unsigned i = address - DMI_DATA0;
 549     if (!abstractcs.busy)
 550       write32(dmdata, address - DMI_DATA0, value);
 551
 552     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 553       abstractcs.cmderr = CMDERR_BUSY;
 554     }
 555
 556     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 557       perform_abstract_command();
 558     }
 559     return true;
 560
 561   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) {
 562     unsigned i = address - DMI_PROGBUF0;
 563
 564     if (!abstractcs.busy)
 565       write32(program_buffer, i, value);
 566
 567     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 568       perform_abstract_command();
 569     }
 570     return true;
 571
 572   } else {
 573     switch (address) {
 574       case DMI_DMCONTROL:
 575         {
 576           if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE))
 577             reset();
 578           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
 579           if (dmcontrol.dmactive) {
 580             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
 581             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
 582             dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET);
 583             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
 584             dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) <<
 585                 DMI_DMCONTROL_HARTSEL_OFFSET);
 586           }
 587           processor_t *proc = current_proc();
 588           if (proc) {
 589             proc->halt_request = dmcontrol.haltreq;
 590             if (dmcontrol.resumereq) {
 591               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
 592               resumeack[dmcontrol.hartsel] = false;
 593             }
 594             if (dmcontrol.hartreset) {
 595               proc->reset();
 596             }
 597           }
 598           if (dmcontrol.ndmreset) {
 599             for (size_t i = 0; i < sim->nprocs(); i++) {
 600               proc = sim->get_core(i);
 601               proc->reset();
 602             }
 603           }
 604         }
 605         return true;
 606
 607       case DMI_COMMAND:
 608         command = value;
 609         return perform_abstract_command();
 610
 611       case DMI_ABSTRACTCS:
 612         abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR))));
 613         return true;
 614
 615       case DMI_ABSTRACTAUTO:
 616         abstractauto.autoexecprogbuf = get_field(value,
 617             DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
 618         abstractauto.autoexecdata = get_field(value,
 619             DMI_ABSTRACTAUTO_AUTOEXECDATA);
 620         return true;
 621       case DMI_SBCS:
 622         sbcs.readonaddr = get_field(value, DMI_SBCS_SBREADONADDR);
 623         sbcs.sbaccess = get_field(value, DMI_SBCS_SBACCESS);
 624         sbcs.autoincrement = get_field(value, DMI_SBCS_SBAUTOINCREMENT);
 625         sbcs.readondata = get_field(value, DMI_SBCS_SBREADONDATA);
 626         sbcs.error &= ~get_field(value, DMI_SBCS_SBERROR);
 627         return true;
 628       case DMI_SBADDRESS0:
 629         sbaddress[0] = value;
 630         if (sbcs.error == 0 && sbcs.readonaddr) {
 631           sb_read();
 632         }
 633         return true;
 634       case DMI_SBADDRESS1:
 635         sbaddress[1] = value;
 636         return true;
 637       case DMI_SBADDRESS2:
 638         sbaddress[2] = value;
 639         return true;
 640       case DMI_SBADDRESS3:
 641         sbaddress[3] = value;
 642         return true;
 643       case DMI_SBDATA0:
 644         sbdata[0] = value;
 645         if (sbcs.error == 0) {
 646           sb_write();
 647           if (sbcs.autoincrement && sbcs.error == 0) {
 648             sb_autoincrement();
 649           }
 650         }
 651         return true;
 652       case DMI_SBDATA1:
 653         sbdata[1] = value;
 654         return true;
 655       case DMI_SBDATA2:
 656         sbdata[2] = value;
 657         return true;
 658       case DMI_SBDATA3:
 659         sbdata[3] = value;
 660         return true;
 661     }
 662   }
 663   return false;
 664 }