riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "debug_defines.h"
   5 #include "opcodes.h"
   6 #include "mmu.h"
   7
   8 #include "debug_rom/debug_rom.h"
   9 #include "debug_rom/debug_rom_defines.h"
  10
  11 #if 1
  12 #  define D(x) x
  13 #else
  14 #  define D(x)
  15 #endif
  16
  17 ///////////////////////// debug_module_t
  18
  19 debug_module_t::debug_module_t(sim_t *sim) : sim(sim)
  20 {
  21   dmcontrol = {0};
  22
  23   dmstatus = {0};
  24   dmstatus.authenticated = 1;
  25   dmstatus.versionlo = 2;
  26
  27   abstractcs = {0};
  28   abstractcs.progsize = progsize;
  29
  30   abstractauto = {0};
  31
  32   memset(halted, 0, sizeof(halted));
  33   memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
  34   memset(resumeack, 0, sizeof(resumeack));
  35   memset(program_buffer, 0, sizeof(program_buffer));
  36   memset(dmdata, 0, sizeof(dmdata));
  37
  38   write32(debug_rom_whereto, 0,
  39           jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO));
  40
  41   memset(debug_abstract, 0, sizeof(debug_abstract));
  42
  43 }
  44
  45 void debug_module_t::reset()
  46 {
  47   for (unsigned i = 0; i < sim->nprocs(); i++) {
  48     processor_t *proc = sim->get_core(i);
  49     if (proc)
  50       proc->halt_request = false;
  51   }
  52
  53   dmcontrol = {0};
  54
  55   dmstatus = {0};
  56   dmstatus.authenticated = 1;
  57   dmstatus.versionlo = 2;
  58
  59   abstractcs = {0};
  60   abstractcs.datacount = sizeof(dmdata) / 4;
  61   abstractcs.progsize = progsize;
  62
  63   abstractauto = {0};
  64 }
  65
  66 void debug_module_t::add_device(bus_t *bus) {
  67   bus->add_device(DEBUG_START, this);
  68 }
  69
  70 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
  71 {
  72   addr = DEBUG_START + addr;
  73
  74   if (addr >= DEBUG_ROM_ENTRY &&
  75       (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) {
  76     memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len);
  77     return true;
  78   }
  79
  80   if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) {
  81     memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len);
  82     return true;
  83   }
  84
  85   if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) {
  86     memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len);
  87     return true;
  88   }
  89
  90   if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) {
  91     memcpy(bytes, debug_abstract + addr - debug_abstract_start, len);
  92     return true;
  93   }
  94
  95   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
  96     memcpy(bytes, dmdata + addr - debug_data_start, len);
  97     return true;
  98   }
  99
 100   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
 101     memcpy(bytes, program_buffer + addr - debug_progbuf_start, len);
 102     return true;
 103   }
 104
 105   fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
 106           PRIx64 "\n", len, addr);
 107
 108   return false;
 109 }
 110
 111 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 112 {
 113
 114   uint8_t id_bytes[4];
 115   uint32_t id = 0;
 116   if (len == 4) {
 117     memcpy(id_bytes, bytes, 4);
 118     id = read32(id_bytes, 0);
 119   }
 120
 121   addr = DEBUG_START + addr;
 122
 123   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 124     memcpy(dmdata + addr - debug_data_start, bytes, len);
 125     return true;
 126   }
 127
 128   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
 129     fprintf(stderr, "Successful write to program buffer %d bytes at %x\n", (int) len, (int) addr);
 130     memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
 131
 132     return true;
 133   }
 134
 135   if (addr == DEBUG_ROM_HALTED) {
 136     assert (len == 4);
 137     halted[id] = true;
 138     if (dmcontrol.hartsel == id) {
 139         if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){
 140           if (dmcontrol.hartsel == id) {
 141               abstractcs.busy = false;
 142           }
 143         }
 144     }
 145     return true;
 146   }
 147
 148   if (addr == DEBUG_ROM_GOING) {
 149     debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO);
 150     return true;
 151   }
 152
 153   if (addr == DEBUG_ROM_RESUMING) {
 154     assert (len == 4);
 155     halted[id] = false;
 156     resumeack[id] = true;
 157     debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME);
 158     return true;
 159   }
 160
 161   if (addr == DEBUG_ROM_EXCEPTION) {
 162     if (abstractcs.cmderr == CMDERR_NONE) {
 163       abstractcs.cmderr = CMDERR_EXCEPTION;
 164     }
 165     return true;
 166   }
 167
 168   fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
 169           PRIx64 "\n", len, addr);
 170   return false;
 171 }
 172
 173 void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value)
 174 {
 175   uint8_t* base = memory + index * 4;
 176   base[0] = value & 0xff;
 177   base[1] = (value >> 8) & 0xff;
 178   base[2] = (value >> 16) & 0xff;
 179   base[3] = (value >> 24) & 0xff;
 180 }
 181
 182 uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index)
 183 {
 184   uint8_t* base = memory + index * 4;
 185   uint32_t value = ((uint32_t) base[0]) |
 186     (((uint32_t) base[1]) << 8) |
 187     (((uint32_t) base[2]) << 16) |
 188     (((uint32_t) base[3]) << 24);
 189   return value;
 190 }
 191
 192 processor_t *debug_module_t::current_proc() const
 193 {
 194   processor_t *proc = NULL;
 195   try {
 196     proc = sim->get_core(dmcontrol.hartsel);
 197   } catch (const std::out_of_range&) {
 198   }
 199   return proc;
 200 }
 201
 202 bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 203 {
 204   uint32_t result = 0;
 205   D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
 206   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 207     unsigned i = address - DMI_DATA0;
 208     result = read32(dmdata, i);
 209
 210     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 211       abstractcs.cmderr = CMDERR_BUSY;
 212     }
 213
 214     if ((abstractauto.autoexecdata >> i) & 1){
 215       perform_abstract_command();
 216     }
 217   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
 218     unsigned i = address - DMI_PROGBUF0;
 219     result = read32(program_buffer, i);
 220     if ((abstractauto.autoexecprogbuf >> i) & 1) {
 221       perform_abstract_command();
 222     }
 223
 224   } else {
 225     switch (address) {
 226       case DMI_DMCONTROL:
 227         {
 228           processor_t *proc = current_proc();
 229           if (proc)
 230             dmcontrol.haltreq = proc->halt_request;
 231
 232           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
 233           result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
 234           result = set_field(result, DMI_DMCONTROL_HARTSEL, dmcontrol.hartsel);
 235           result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
 236           result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
 237           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
 238         }
 239         break;
 240       case DMI_DMSTATUS:
 241         {
 242           processor_t *proc = current_proc();
 243
 244           dmstatus.allnonexistant = false;
 245           dmstatus.allunavail = false;
 246           dmstatus.allrunning = false;
 247           dmstatus.allhalted = false;
 248           dmstatus.allresumeack = false;
 249           if (proc) {
 250             if (halted[dmcontrol.hartsel]) {
 251               dmstatus.allhalted = true;
 252             } else {
 253               dmstatus.allrunning = true;
 254             }
 255           } else {
 256             dmstatus.allnonexistant = true;
 257           }
 258           dmstatus.anynonexistant = dmstatus.allnonexistant;
 259           dmstatus.anyunavail = dmstatus.allunavail;
 260           dmstatus.anyrunning = dmstatus.allrunning;
 261           dmstatus.anyhalted = dmstatus.allhalted;
 262           if (proc) {
 263             if (resumeack[dmcontrol.hartsel]) {
 264               dmstatus.allresumeack = true;
 265             } else {
 266               dmstatus.allresumeack = false;
 267             }
 268           } else {
 269             dmstatus.allresumeack = false;
 270           }
 271
 272           result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
 273           result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
 274           result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
 275           result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted);
 276           result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack);
 277           result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant);
 278           result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail);
 279           result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning);
 280           result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted);
 281           result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack);
 282           result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated);
 283           result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy);
 284           result = set_field(result, DMI_DMSTATUS_VERSIONHI, dmstatus.versionhi);
 285           result = set_field(result, DMI_DMSTATUS_VERSIONLO, dmstatus.versionlo);
 286         }
 287         break;
 288       case DMI_ABSTRACTCS:
 289         result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr);
 290         result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy);
 291         result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount);
 292         result = set_field(result, DMI_ABSTRACTCS_PROGSIZE, abstractcs.progsize);
 293         break;
 294       case DMI_ABSTRACTAUTO:
 295         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf);
 296         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata);
 297         break;
 298       case DMI_COMMAND:
 299         result = 0;
 300         break;
 301       case DMI_HARTINFO:
 302         result = set_field(result, DMI_HARTINFO_NSCRATCH, 1);
 303         result = set_field(result, DMI_HARTINFO_DATAACCESS, 1);
 304         result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount);
 305         result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start);
 306         break;
 307       default:
 308         result = 0;
 309         D(fprintf(stderr, "Unexpected. Returning Error."));
 310         return false;
 311     }
 312   }
 313   D(fprintf(stderr, "0x%x\n", result));
 314   *value = result;
 315   return true;
 316 }
 317
 318 bool debug_module_t::perform_abstract_command()
 319 {
 320   if (abstractcs.cmderr != CMDERR_NONE)
 321     return true;
 322   if (abstractcs.busy) {
 323     abstractcs.cmderr = CMDERR_BUSY;
 324     return true;
 325   }
 326
 327   if ((command >> 24) == 0) {
 328     // register access
 329     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
 330     bool write = get_field(command, AC_ACCESS_REGISTER_WRITE);
 331     unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO);
 332
 333     if (!halted[dmcontrol.hartsel]) {
 334       abstractcs.cmderr = CMDERR_HALTRESUME;
 335       return true;
 336     }
 337
 338     if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
 339
 340       if (regno < 0x1000 || regno >= 0x1020) {
 341         abstractcs.cmderr = CMDERR_NOTSUP;
 342         return true;
 343       }
 344
 345       unsigned regnum = regno - 0x1000;
 346
 347       switch (size) {
 348       case 2:
 349         if (write)
 350           write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
 351         else
 352           write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
 353         break;
 354       case 3:
 355         if (write)
 356           write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
 357         else
 358           write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
 359         break;
 360         /*
 361           case 4:
 362           if (write)
 363           write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
 364           else
 365           write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
 366           break;
 367         */
 368       default:
 369         abstractcs.cmderr = CMDERR_NOTSUP;
 370         return true;
 371       }
 372     } else {
 373       //NOP
 374       write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
 375     }
 376
 377     if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
 378       // Since the next instruction is what we will use, just use nother NOP
 379       // to get there.
 380       write32(debug_abstract, 1, addi(ZERO, ZERO, 0));
 381     } else {
 382       write32(debug_abstract, 1, ebreak());
 383     }
 384
 385     debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
 386
 387     abstractcs.busy = true;
 388   } else {
 389     abstractcs.cmderr = CMDERR_NOTSUP;
 390   }
 391   return true;
 392 }
 393
 394 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 395 {
 396   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
 397   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 398     unsigned i = address - DMI_DATA0;
 399     write32(dmdata, address - DMI_DATA0, value);
 400
 401     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 402       abstractcs.cmderr = CMDERR_BUSY;
 403     }
 404
 405     if ((abstractauto.autoexecdata >> i) & 1) {
 406       perform_abstract_command();
 407     }
 408     return true;
 409
 410   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
 411     unsigned i = address - DMI_PROGBUF0;
 412
 413     write32(program_buffer, i, value);
 414
 415     if ((abstractauto.autoexecprogbuf >> i) & 1) {
 416       perform_abstract_command();
 417     }
 418     return true;
 419
 420   } else {
 421     switch (address) {
 422       case DMI_DMCONTROL:
 423         {
 424           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
 425           if (dmcontrol.dmactive) {
 426             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
 427             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
 428             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
 429             dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
 430           } else {
 431             reset();
 432           }
 433           processor_t *proc = current_proc();
 434           if (proc) {
 435             proc->halt_request = dmcontrol.haltreq;
 436             if (dmcontrol.resumereq) {
 437               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
 438               resumeack[dmcontrol.hartsel] = false;
 439             }
 440           }
 441         }
 442         return true;
 443
 444       case DMI_COMMAND:
 445         command = value;
 446         return perform_abstract_command();
 447
 448       case DMI_ABSTRACTCS:
 449         abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR))));
 450         return true;
 451
 452       case DMI_ABSTRACTAUTO:
 453         abstractauto.autoexecprogbuf = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
 454         abstractauto.autoexecdata = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECDATA);
 455         break;
 456     }
 457   }
 458   return false;
 459 }