riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "debug_defines.h"
   5 #include "opcodes.h"
   6 #include "mmu.h"
   7
   8 #include "debug_rom/debug_rom.h"
   9 #include "debug_rom/debug_rom_defines.h"
  10
  11 #if 0
  12 #  define D(x) x
  13 #else
  14 #  define D(x)
  15 #endif
  16
  17 ///////////////////////// debug_module_t
  18
  19 debug_module_t::debug_module_t(sim_t *sim) : sim(sim)
  20 {
  21   dmcontrol = {0};
  22
  23   dmstatus = {0};
  24   dmstatus.authenticated = 1;
  25   dmstatus.versionlo = 2;
  26
  27   abstractcs = {0};
  28   abstractcs.progsize = progsize;
  29
  30   abstractauto = {0};
  31
  32   memset(halted, 0, sizeof(halted));
  33   memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
  34   memset(resumeack, 0, sizeof(resumeack));
  35   memset(program_buffer, 0, sizeof(program_buffer));
  36   memset(dmdata, 0, sizeof(dmdata));
  37
  38   write32(debug_rom_whereto, 0,
  39           jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO));
  40
  41   memset(debug_abstract, 0, sizeof(debug_abstract));
  42
  43 }
  44
  45 void debug_module_t::reset()
  46 {
  47   for (unsigned i = 0; i < sim->nprocs(); i++) {
  48     processor_t *proc = sim->get_core(i);
  49     if (proc)
  50       proc->halt_request = false;
  51   }
  52
  53   dmcontrol = {0};
  54
  55   dmstatus = {0};
  56   dmstatus.authenticated = 1;
  57   dmstatus.versionlo = 2;
  58
  59   abstractcs = {0};
  60   abstractcs.datacount = sizeof(dmdata) / 4;
  61   abstractcs.progsize = progsize;
  62
  63   abstractauto = {0};
  64 }
  65
  66 void debug_module_t::add_device(bus_t *bus) {
  67   bus->add_device(DEBUG_START, this);
  68 }
  69
  70 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
  71 {
  72   addr = DEBUG_START + addr;
  73
  74   if (addr >= DEBUG_ROM_ENTRY &&
  75       (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) {
  76     memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len);
  77     return true;
  78   }
  79
  80   if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) {
  81     memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len);
  82     return true;
  83   }
  84
  85   if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) {
  86     memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len);
  87     return true;
  88   }
  89
  90   if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) {
  91     memcpy(bytes, debug_abstract + addr - debug_abstract_start, len);
  92     return true;
  93   }
  94
  95   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
  96     memcpy(bytes, dmdata + addr - debug_data_start, len);
  97     return true;
  98   }
  99
 100   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
 101     memcpy(bytes, program_buffer + addr - debug_progbuf_start, len);
 102     return true;
 103   }
 104
 105   fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
 106           PRIx64 "\n", len, addr);
 107
 108   return false;
 109 }
 110
 111 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 112 {
 113   D(
 114       switch (len) {
 115         case 4:
 116           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); "
 117               "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes,
 118               dmcontrol.hartsel);
 119           break;
 120         default:
 121           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); "
 122               "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel);
 123           break;
 124       }
 125    );
 126
 127   uint8_t id_bytes[4];
 128   uint32_t id = 0;
 129   if (len == 4) {
 130     memcpy(id_bytes, bytes, 4);
 131     id = read32(id_bytes, 0);
 132   }
 133
 134   addr = DEBUG_START + addr;
 135
 136   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 137     memcpy(dmdata + addr - debug_data_start, bytes, len);
 138     return true;
 139   }
 140
 141   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
 142     memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
 143
 144     return true;
 145   }
 146
 147   if (addr == DEBUG_ROM_HALTED) {
 148     assert (len == 4);
 149     halted[id] = true;
 150     if (dmcontrol.hartsel == id) {
 151         if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){
 152           if (dmcontrol.hartsel == id) {
 153               abstractcs.busy = false;
 154           }
 155         }
 156     }
 157     return true;
 158   }
 159
 160   if (addr == DEBUG_ROM_GOING) {
 161     debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO);
 162     return true;
 163   }
 164
 165   if (addr == DEBUG_ROM_RESUMING) {
 166     assert (len == 4);
 167     halted[id] = false;
 168     resumeack[id] = true;
 169     debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME);
 170     return true;
 171   }
 172
 173   if (addr == DEBUG_ROM_EXCEPTION) {
 174     if (abstractcs.cmderr == CMDERR_NONE) {
 175       abstractcs.cmderr = CMDERR_EXCEPTION;
 176     }
 177     return true;
 178   }
 179
 180   fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
 181           PRIx64 "\n", len, addr);
 182   return false;
 183 }
 184
 185 void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value)
 186 {
 187   uint8_t* base = memory + index * 4;
 188   base[0] = value & 0xff;
 189   base[1] = (value >> 8) & 0xff;
 190   base[2] = (value >> 16) & 0xff;
 191   base[3] = (value >> 24) & 0xff;
 192 }
 193
 194 uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index)
 195 {
 196   uint8_t* base = memory + index * 4;
 197   uint32_t value = ((uint32_t) base[0]) |
 198     (((uint32_t) base[1]) << 8) |
 199     (((uint32_t) base[2]) << 16) |
 200     (((uint32_t) base[3]) << 24);
 201   return value;
 202 }
 203
 204 processor_t *debug_module_t::current_proc() const
 205 {
 206   processor_t *proc = NULL;
 207   try {
 208     proc = sim->get_core(dmcontrol.hartsel);
 209   } catch (const std::out_of_range&) {
 210   }
 211   return proc;
 212 }
 213
 214 bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 215 {
 216   uint32_t result = 0;
 217   D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
 218   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 219     unsigned i = address - DMI_DATA0;
 220     result = read32(dmdata, i);
 221     if (abstractcs.busy) {
 222       result = -1;
 223       fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 224     }
 225
 226     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 227       abstractcs.cmderr = CMDERR_BUSY;
 228     }
 229
 230     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 231       perform_abstract_command();
 232     }
 233   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
 234     unsigned i = address - DMI_PROGBUF0;
 235     result = read32(program_buffer, i);
 236     if (abstractcs.busy) {
 237       result = -1;
 238       fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 239     }
 240     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 241       perform_abstract_command();
 242     }
 243
 244   } else {
 245     switch (address) {
 246       case DMI_DMCONTROL:
 247         {
 248           processor_t *proc = current_proc();
 249           if (proc)
 250             dmcontrol.haltreq = proc->halt_request;
 251
 252           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
 253           result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
 254           result = set_field(result, DMI_DMCONTROL_HARTSEL, dmcontrol.hartsel);
 255           result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
 256           result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
 257           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
 258         }
 259         break;
 260       case DMI_DMSTATUS:
 261         {
 262           processor_t *proc = current_proc();
 263
 264           dmstatus.allnonexistant = false;
 265           dmstatus.allunavail = false;
 266           dmstatus.allrunning = false;
 267           dmstatus.allhalted = false;
 268           dmstatus.allresumeack = false;
 269           if (proc) {
 270             if (halted[dmcontrol.hartsel]) {
 271               dmstatus.allhalted = true;
 272             } else {
 273               dmstatus.allrunning = true;
 274             }
 275           } else {
 276             dmstatus.allnonexistant = true;
 277           }
 278           dmstatus.anynonexistant = dmstatus.allnonexistant;
 279           dmstatus.anyunavail = dmstatus.allunavail;
 280           dmstatus.anyrunning = dmstatus.allrunning;
 281           dmstatus.anyhalted = dmstatus.allhalted;
 282           if (proc) {
 283             if (resumeack[dmcontrol.hartsel]) {
 284               dmstatus.allresumeack = true;
 285             } else {
 286               dmstatus.allresumeack = false;
 287             }
 288           } else {
 289             dmstatus.allresumeack = false;
 290           }
 291
 292           result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
 293           result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
 294           result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
 295           result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted);
 296           result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack);
 297           result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant);
 298           result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail);
 299           result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning);
 300           result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted);
 301           result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack);
 302           result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated);
 303           result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy);
 304           result = set_field(result, DMI_DMSTATUS_VERSIONHI, dmstatus.versionhi);
 305           result = set_field(result, DMI_DMSTATUS_VERSIONLO, dmstatus.versionlo);
 306         }
 307         break;
 308       case DMI_ABSTRACTCS:
 309         result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr);
 310         result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy);
 311         result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount);
 312         result = set_field(result, DMI_ABSTRACTCS_PROGSIZE, abstractcs.progsize);
 313         break;
 314       case DMI_ABSTRACTAUTO:
 315         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf);
 316         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata);
 317         break;
 318       case DMI_COMMAND:
 319         result = 0;
 320         break;
 321       case DMI_HARTINFO:
 322         result = set_field(result, DMI_HARTINFO_NSCRATCH, 1);
 323         result = set_field(result, DMI_HARTINFO_DATAACCESS, 1);
 324         result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount);
 325         result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start);
 326         break;
 327       default:
 328         result = 0;
 329         D(fprintf(stderr, "Unexpected. Returning Error."));
 330         return false;
 331     }
 332   }
 333   D(fprintf(stderr, "0x%x\n", result));
 334   *value = result;
 335   return true;
 336 }
 337
 338 bool debug_module_t::perform_abstract_command()
 339 {
 340   if (abstractcs.cmderr != CMDERR_NONE)
 341     return true;
 342   if (abstractcs.busy) {
 343     abstractcs.cmderr = CMDERR_BUSY;
 344     return true;
 345   }
 346
 347   if ((command >> 24) == 0) {
 348     // register access
 349     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
 350     bool write = get_field(command, AC_ACCESS_REGISTER_WRITE);
 351     unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO);
 352
 353     if (!halted[dmcontrol.hartsel]) {
 354       abstractcs.cmderr = CMDERR_HALTRESUME;
 355       return true;
 356     }
 357
 358     if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
 359
 360       if (regno < 0x1000 || regno >= 0x1020) {
 361         abstractcs.cmderr = CMDERR_NOTSUP;
 362         return true;
 363       }
 364
 365       unsigned regnum = regno - 0x1000;
 366
 367       switch (size) {
 368       case 2:
 369         if (write)
 370           write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
 371         else
 372           write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
 373         break;
 374       case 3:
 375         if (write)
 376           write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
 377         else
 378           write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
 379         break;
 380         /*
 381           case 4:
 382           if (write)
 383           write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
 384           else
 385           write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
 386           break;
 387         */
 388       default:
 389         abstractcs.cmderr = CMDERR_NOTSUP;
 390         return true;
 391       }
 392     } else {
 393       //NOP
 394       write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
 395     }
 396
 397     if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
 398       // Since the next instruction is what we will use, just use nother NOP
 399       // to get there.
 400       write32(debug_abstract, 1, addi(ZERO, ZERO, 0));
 401     } else {
 402       write32(debug_abstract, 1, ebreak());
 403     }
 404
 405     debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
 406
 407     abstractcs.busy = true;
 408   } else {
 409     abstractcs.cmderr = CMDERR_NOTSUP;
 410   }
 411   return true;
 412 }
 413
 414 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 415 {
 416   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
 417   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 418     unsigned i = address - DMI_DATA0;
 419     if (!abstractcs.busy)
 420       write32(dmdata, address - DMI_DATA0, value);
 421
 422     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 423       abstractcs.cmderr = CMDERR_BUSY;
 424     }
 425
 426     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 427       perform_abstract_command();
 428     }
 429     return true;
 430
 431   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
 432     unsigned i = address - DMI_PROGBUF0;
 433
 434     if (!abstractcs.busy)
 435       write32(program_buffer, i, value);
 436
 437     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 438       perform_abstract_command();
 439     }
 440     return true;
 441
 442   } else {
 443     switch (address) {
 444       case DMI_DMCONTROL:
 445         {
 446           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
 447           if (dmcontrol.dmactive) {
 448             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
 449             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
 450             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
 451             dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
 452           } else {
 453             reset();
 454           }
 455           processor_t *proc = current_proc();
 456           if (proc) {
 457             proc->halt_request = dmcontrol.haltreq;
 458             if (dmcontrol.resumereq) {
 459               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
 460               resumeack[dmcontrol.hartsel] = false;
 461             }
 462             if (dmcontrol.ndmreset) {
 463               proc->reset();
 464             }
 465           }
 466         }
 467         return true;
 468
 469       case DMI_COMMAND:
 470         command = value;
 471         return perform_abstract_command();
 472
 473       case DMI_ABSTRACTCS:
 474         abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR))));
 475         return true;
 476
 477       case DMI_ABSTRACTAUTO:
 478         abstractauto.autoexecprogbuf = get_field(value,
 479             DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
 480         abstractauto.autoexecdata = get_field(value,
 481             DMI_ABSTRACTAUTO_AUTOEXECDATA);
 482         return true;
 483     }
 484   }
 485   return false;
 486 }