3 #include "debug_module.h"
4 #include "debug_defines.h"
8 #include "debug_rom/debug_rom.h"
9 #include "debug_rom/debug_rom_defines.h"
17 ///////////////////////// debug_module_t
19 debug_module_t::debug_module_t(sim_t
*sim
, unsigned progbufsize
, unsigned max_bus_master_bits
,
20 bool require_authentication
) :
21 progbufsize(progbufsize
),
22 program_buffer_bytes(4 + 4*progbufsize
),
23 max_bus_master_bits(max_bus_master_bits
),
24 require_authentication(require_authentication
),
25 debug_progbuf_start(debug_data_start
- program_buffer_bytes
),
26 debug_abstract_start(debug_progbuf_start
- debug_abstract_size
*4),
29 program_buffer
= new uint8_t[program_buffer_bytes
];
31 memset(halted
, 0, sizeof(halted
));
32 memset(debug_rom_flags
, 0, sizeof(debug_rom_flags
));
33 memset(resumeack
, 0, sizeof(resumeack
));
34 memset(program_buffer
, 0, program_buffer_bytes
);
35 program_buffer
[4*progbufsize
] = ebreak();
36 program_buffer
[4*progbufsize
+1] = ebreak() >> 8;
37 program_buffer
[4*progbufsize
+2] = ebreak() >> 16;
38 program_buffer
[4*progbufsize
+3] = ebreak() >> 24;
39 memset(dmdata
, 0, sizeof(dmdata
));
41 write32(debug_rom_whereto
, 0,
42 jal(ZERO
, debug_abstract_start
- DEBUG_ROM_WHERETO
));
44 memset(debug_abstract
, 0, sizeof(debug_abstract
));
49 debug_module_t::~debug_module_t()
51 delete[] program_buffer
;
54 void debug_module_t::reset()
56 for (unsigned i
= 0; i
< sim
->nprocs(); i
++) {
57 processor_t
*proc
= sim
->get_core(i
);
59 proc
->halt_request
= false;
65 dmstatus
.impebreak
= true;
66 dmstatus
.authenticated
= !require_authentication
;
70 abstractcs
.datacount
= sizeof(dmdata
) / 4;
71 abstractcs
.progbufsize
= progbufsize
;
76 if (max_bus_master_bits
> 0) {
78 sbcs
.asize
= sizeof(reg_t
) * 8;
80 if (max_bus_master_bits
>= 64)
82 if (max_bus_master_bits
>= 32)
84 if (max_bus_master_bits
>= 16)
86 if (max_bus_master_bits
>= 8)
92 void debug_module_t::add_device(bus_t
*bus
) {
93 bus
->add_device(DEBUG_START
, this);
96 bool debug_module_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
98 addr
= DEBUG_START
+ addr
;
100 if (addr
>= DEBUG_ROM_ENTRY
&&
101 (addr
+ len
) <= (DEBUG_ROM_ENTRY
+ debug_rom_raw_len
)) {
102 memcpy(bytes
, debug_rom_raw
+ addr
- DEBUG_ROM_ENTRY
, len
);
106 if (addr
>= DEBUG_ROM_WHERETO
&& (addr
+ len
) <= (DEBUG_ROM_WHERETO
+ 4)) {
107 memcpy(bytes
, debug_rom_whereto
+ addr
- DEBUG_ROM_WHERETO
, len
);
111 if (addr
>= DEBUG_ROM_FLAGS
&& ((addr
+ len
) <= DEBUG_ROM_FLAGS
+ 1024)) {
112 memcpy(bytes
, debug_rom_flags
+ addr
- DEBUG_ROM_FLAGS
, len
);
116 if (addr
>= debug_abstract_start
&& ((addr
+ len
) <= (debug_abstract_start
+ sizeof(debug_abstract
)))) {
117 memcpy(bytes
, debug_abstract
+ addr
- debug_abstract_start
, len
);
121 if (addr
>= debug_data_start
&& (addr
+ len
) <= (debug_data_start
+ sizeof(dmdata
))) {
122 memcpy(bytes
, dmdata
+ addr
- debug_data_start
, len
);
126 if (addr
>= debug_progbuf_start
&& ((addr
+ len
) <= (debug_progbuf_start
+ program_buffer_bytes
))) {
127 memcpy(bytes
, program_buffer
+ addr
- debug_progbuf_start
, len
);
131 fprintf(stderr
, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
132 PRIx64
"\n", len
, addr
);
137 bool debug_module_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
142 fprintf(stderr
, "store(addr=0x%lx, len=%d, bytes=0x%08x); "
143 "hartsel=0x%x\n", addr
, (unsigned) len
, *(uint32_t *) bytes
,
147 fprintf(stderr
, "store(addr=0x%lx, len=%d, bytes=...); "
148 "hartsel=0x%x\n", addr
, (unsigned) len
, dmcontrol
.hartsel
);
156 memcpy(id_bytes
, bytes
, 4);
157 id
= read32(id_bytes
, 0);
160 addr
= DEBUG_START
+ addr
;
162 if (addr
>= debug_data_start
&& (addr
+ len
) <= (debug_data_start
+ sizeof(dmdata
))) {
163 memcpy(dmdata
+ addr
- debug_data_start
, bytes
, len
);
167 if (addr
>= debug_progbuf_start
&& ((addr
+ len
) <= (debug_progbuf_start
+ program_buffer_bytes
))) {
168 memcpy(program_buffer
+ addr
- debug_progbuf_start
, bytes
, len
);
173 if (addr
== DEBUG_ROM_HALTED
) {
176 if (dmcontrol
.hartsel
== id
) {
177 if (0 == (debug_rom_flags
[id
] & (1 << DEBUG_ROM_FLAG_GO
))){
178 if (dmcontrol
.hartsel
== id
) {
179 abstractcs
.busy
= false;
186 if (addr
== DEBUG_ROM_GOING
) {
187 debug_rom_flags
[dmcontrol
.hartsel
] &= ~(1 << DEBUG_ROM_FLAG_GO
);
191 if (addr
== DEBUG_ROM_RESUMING
) {
194 resumeack
[id
] = true;
195 debug_rom_flags
[id
] &= ~(1 << DEBUG_ROM_FLAG_RESUME
);
199 if (addr
== DEBUG_ROM_EXCEPTION
) {
200 if (abstractcs
.cmderr
== CMDERR_NONE
) {
201 abstractcs
.cmderr
= CMDERR_EXCEPTION
;
206 fprintf(stderr
, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
207 PRIx64
"\n", len
, addr
);
211 void debug_module_t::write32(uint8_t *memory
, unsigned int index
, uint32_t value
)
213 uint8_t* base
= memory
+ index
* 4;
214 base
[0] = value
& 0xff;
215 base
[1] = (value
>> 8) & 0xff;
216 base
[2] = (value
>> 16) & 0xff;
217 base
[3] = (value
>> 24) & 0xff;
220 uint32_t debug_module_t::read32(uint8_t *memory
, unsigned int index
)
222 uint8_t* base
= memory
+ index
* 4;
223 uint32_t value
= ((uint32_t) base
[0]) |
224 (((uint32_t) base
[1]) << 8) |
225 (((uint32_t) base
[2]) << 16) |
226 (((uint32_t) base
[3]) << 24);
230 processor_t
*debug_module_t::current_proc() const
232 processor_t
*proc
= NULL
;
234 proc
= sim
->get_core(dmcontrol
.hartsel
);
235 } catch (const std::out_of_range
&) {
240 unsigned debug_module_t::sb_access_bits()
242 return 8 << sbcs
.sbaccess
;
245 void debug_module_t::sb_autoincrement()
247 if (!sbcs
.autoincrement
|| !max_bus_master_bits
)
250 uint64_t value
= sbaddress
[0] + sb_access_bits() / 8;
251 sbaddress
[0] = value
;
252 uint32_t carry
= value
>> 32;
254 value
= sbaddress
[1] + carry
;
255 sbaddress
[1] = value
;
258 value
= sbaddress
[2] + carry
;
259 sbaddress
[2] = value
;
262 sbaddress
[3] += carry
;
265 void debug_module_t::sb_read()
267 reg_t address
= ((uint64_t) sbaddress
[1] << 32) | sbaddress
[0];
269 if (sbcs
.sbaccess
== 0 && max_bus_master_bits
>= 8) {
270 sbdata
[0] = sim
->debug_mmu
->load_uint8(address
);
271 } else if (sbcs
.sbaccess
== 1 && max_bus_master_bits
>= 16) {
272 sbdata
[0] = sim
->debug_mmu
->load_uint16(address
);
273 } else if (sbcs
.sbaccess
== 2 && max_bus_master_bits
>= 32) {
274 sbdata
[0] = sim
->debug_mmu
->load_uint32(address
);
275 } else if (sbcs
.sbaccess
== 3 && max_bus_master_bits
>= 64) {
276 uint64_t value
= sim
->debug_mmu
->load_uint32(address
);
278 sbdata
[1] = value
>> 32;
282 } catch (trap_load_access_fault
& t
) {
287 void debug_module_t::sb_write()
289 reg_t address
= ((uint64_t) sbaddress
[1] << 32) | sbaddress
[0];
290 D(fprintf(stderr
, "sb_write() 0x%x @ 0x%lx\n", sbdata
[0], address
));
291 if (sbcs
.sbaccess
== 0 && max_bus_master_bits
>= 8) {
292 sim
->debug_mmu
->store_uint8(address
, sbdata
[0]);
293 } else if (sbcs
.sbaccess
== 1 && max_bus_master_bits
>= 16) {
294 sim
->debug_mmu
->store_uint16(address
, sbdata
[0]);
295 } else if (sbcs
.sbaccess
== 2 && max_bus_master_bits
>= 32) {
296 sim
->debug_mmu
->store_uint32(address
, sbdata
[0]);
297 } else if (sbcs
.sbaccess
== 3 && max_bus_master_bits
>= 64) {
298 sim
->debug_mmu
->store_uint64(address
,
299 (((uint64_t) sbdata
[1]) << 32) | sbdata
[0]);
305 bool debug_module_t::dmi_read(unsigned address
, uint32_t *value
)
308 D(fprintf(stderr
, "dmi_read(0x%x) -> ", address
));
309 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
310 unsigned i
= address
- DMI_DATA0
;
311 result
= read32(dmdata
, i
);
312 if (abstractcs
.busy
) {
314 fprintf(stderr
, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address
, i
);
317 if (abstractcs
.busy
&& abstractcs
.cmderr
== CMDERR_NONE
) {
318 abstractcs
.cmderr
= CMDERR_BUSY
;
321 if (!abstractcs
.busy
&& ((abstractauto
.autoexecdata
>> i
) & 1)) {
322 perform_abstract_command();
324 } else if (address
>= DMI_PROGBUF0
&& address
< DMI_PROGBUF0
+ progbufsize
) {
325 unsigned i
= address
- DMI_PROGBUF0
;
326 result
= read32(program_buffer
, i
);
327 if (abstractcs
.busy
) {
329 fprintf(stderr
, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address
, i
);
331 if (!abstractcs
.busy
&& ((abstractauto
.autoexecprogbuf
>> i
) & 1)) {
332 perform_abstract_command();
339 processor_t
*proc
= current_proc();
341 dmcontrol
.haltreq
= proc
->halt_request
;
343 result
= set_field(result
, DMI_DMCONTROL_HALTREQ
, dmcontrol
.haltreq
);
344 result
= set_field(result
, DMI_DMCONTROL_RESUMEREQ
, dmcontrol
.resumereq
);
345 result
= set_field(result
, ((1L<<hartsellen
)-1) <<
346 DMI_DMCONTROL_HARTSEL_OFFSET
, dmcontrol
.hartsel
);
347 result
= set_field(result
, DMI_DMCONTROL_HARTRESET
, dmcontrol
.hartreset
);
348 result
= set_field(result
, DMI_DMCONTROL_NDMRESET
, dmcontrol
.ndmreset
);
349 result
= set_field(result
, DMI_DMCONTROL_DMACTIVE
, dmcontrol
.dmactive
);
354 processor_t
*proc
= current_proc();
356 dmstatus
.allnonexistant
= false;
357 dmstatus
.allunavail
= false;
358 dmstatus
.allrunning
= false;
359 dmstatus
.allhalted
= false;
360 dmstatus
.allresumeack
= false;
362 if (halted
[dmcontrol
.hartsel
]) {
363 dmstatus
.allhalted
= true;
365 dmstatus
.allrunning
= true;
368 dmstatus
.allnonexistant
= true;
370 dmstatus
.anynonexistant
= dmstatus
.allnonexistant
;
371 dmstatus
.anyunavail
= dmstatus
.allunavail
;
372 dmstatus
.anyrunning
= dmstatus
.allrunning
;
373 dmstatus
.anyhalted
= dmstatus
.allhalted
;
375 if (resumeack
[dmcontrol
.hartsel
]) {
376 dmstatus
.allresumeack
= true;
378 dmstatus
.allresumeack
= false;
381 dmstatus
.allresumeack
= false;
384 result
= set_field(result
, DMI_DMSTATUS_IMPEBREAK
,
386 result
= set_field(result
, DMI_DMSTATUS_ALLNONEXISTENT
, dmstatus
.allnonexistant
);
387 result
= set_field(result
, DMI_DMSTATUS_ALLUNAVAIL
, dmstatus
.allunavail
);
388 result
= set_field(result
, DMI_DMSTATUS_ALLRUNNING
, dmstatus
.allrunning
);
389 result
= set_field(result
, DMI_DMSTATUS_ALLHALTED
, dmstatus
.allhalted
);
390 result
= set_field(result
, DMI_DMSTATUS_ALLRESUMEACK
, dmstatus
.allresumeack
);
391 result
= set_field(result
, DMI_DMSTATUS_ANYNONEXISTENT
, dmstatus
.anynonexistant
);
392 result
= set_field(result
, DMI_DMSTATUS_ANYUNAVAIL
, dmstatus
.anyunavail
);
393 result
= set_field(result
, DMI_DMSTATUS_ANYRUNNING
, dmstatus
.anyrunning
);
394 result
= set_field(result
, DMI_DMSTATUS_ANYHALTED
, dmstatus
.anyhalted
);
395 result
= set_field(result
, DMI_DMSTATUS_ANYRESUMEACK
, dmstatus
.anyresumeack
);
396 result
= set_field(result
, DMI_DMSTATUS_AUTHENTICATED
, dmstatus
.authenticated
);
397 result
= set_field(result
, DMI_DMSTATUS_AUTHBUSY
, dmstatus
.authbusy
);
398 result
= set_field(result
, DMI_DMSTATUS_VERSION
, dmstatus
.version
);
402 result
= set_field(result
, DMI_ABSTRACTCS_CMDERR
, abstractcs
.cmderr
);
403 result
= set_field(result
, DMI_ABSTRACTCS_BUSY
, abstractcs
.busy
);
404 result
= set_field(result
, DMI_ABSTRACTCS_DATACOUNT
, abstractcs
.datacount
);
405 result
= set_field(result
, DMI_ABSTRACTCS_PROGBUFSIZE
,
406 abstractcs
.progbufsize
);
408 case DMI_ABSTRACTAUTO
:
409 result
= set_field(result
, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF
, abstractauto
.autoexecprogbuf
);
410 result
= set_field(result
, DMI_ABSTRACTAUTO_AUTOEXECDATA
, abstractauto
.autoexecdata
);
416 result
= set_field(result
, DMI_HARTINFO_NSCRATCH
, 1);
417 result
= set_field(result
, DMI_HARTINFO_DATAACCESS
, 1);
418 result
= set_field(result
, DMI_HARTINFO_DATASIZE
, abstractcs
.datacount
);
419 result
= set_field(result
, DMI_HARTINFO_DATAADDR
, debug_data_start
);
422 result
= set_field(result
, DMI_SBCS_SBVERSION
, sbcs
.version
);
423 result
= set_field(result
, DMI_SBCS_SBREADONADDR
, sbcs
.readonaddr
);
424 result
= set_field(result
, DMI_SBCS_SBACCESS
, sbcs
.sbaccess
);
425 result
= set_field(result
, DMI_SBCS_SBAUTOINCREMENT
, sbcs
.autoincrement
);
426 result
= set_field(result
, DMI_SBCS_SBREADONDATA
, sbcs
.readondata
);
427 result
= set_field(result
, DMI_SBCS_SBERROR
, sbcs
.error
);
428 result
= set_field(result
, DMI_SBCS_SBASIZE
, sbcs
.asize
);
429 result
= set_field(result
, DMI_SBCS_SBACCESS128
, sbcs
.access128
);
430 result
= set_field(result
, DMI_SBCS_SBACCESS64
, sbcs
.access64
);
431 result
= set_field(result
, DMI_SBCS_SBACCESS32
, sbcs
.access32
);
432 result
= set_field(result
, DMI_SBCS_SBACCESS16
, sbcs
.access16
);
433 result
= set_field(result
, DMI_SBCS_SBACCESS8
, sbcs
.access8
);
436 result
= sbaddress
[0];
439 result
= sbaddress
[1];
442 result
= sbaddress
[2];
445 result
= sbaddress
[3];
449 if (sbcs
.error
== 0) {
451 if (sbcs
.readondata
) {
470 D(fprintf(stderr
, "Unexpected. Returning Error."));
474 D(fprintf(stderr
, "0x%x\n", result
));
479 bool debug_module_t::perform_abstract_command()
481 if (abstractcs
.cmderr
!= CMDERR_NONE
)
483 if (abstractcs
.busy
) {
484 abstractcs
.cmderr
= CMDERR_BUSY
;
488 if ((command
>> 24) == 0) {
490 unsigned size
= get_field(command
, AC_ACCESS_REGISTER_SIZE
);
491 bool write
= get_field(command
, AC_ACCESS_REGISTER_WRITE
);
492 unsigned regno
= get_field(command
, AC_ACCESS_REGISTER_REGNO
);
494 if (!halted
[dmcontrol
.hartsel
]) {
495 abstractcs
.cmderr
= CMDERR_HALTRESUME
;
499 if (get_field(command
, AC_ACCESS_REGISTER_TRANSFER
)) {
501 if (regno
< 0x1000 || regno
>= 0x1020) {
502 abstractcs
.cmderr
= CMDERR_NOTSUP
;
506 unsigned regnum
= regno
- 0x1000;
511 write32(debug_abstract
, 0, lw(regnum
, ZERO
, debug_data_start
));
513 write32(debug_abstract
, 0, sw(regnum
, ZERO
, debug_data_start
));
517 write32(debug_abstract
, 0, ld(regnum
, ZERO
, debug_data_start
));
519 write32(debug_abstract
, 0, sd(regnum
, ZERO
, debug_data_start
));
524 write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
526 write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
530 abstractcs
.cmderr
= CMDERR_NOTSUP
;
535 write32(debug_abstract
, 0, addi(ZERO
, ZERO
, 0));
538 if (get_field(command
, AC_ACCESS_REGISTER_POSTEXEC
)) {
539 // Since the next instruction is what we will use, just use nother NOP
541 write32(debug_abstract
, 1, addi(ZERO
, ZERO
, 0));
543 write32(debug_abstract
, 1, ebreak());
546 debug_rom_flags
[dmcontrol
.hartsel
] |= 1 << DEBUG_ROM_FLAG_GO
;
548 abstractcs
.busy
= true;
550 abstractcs
.cmderr
= CMDERR_NOTSUP
;
555 bool debug_module_t::dmi_write(unsigned address
, uint32_t value
)
557 D(fprintf(stderr
, "dmi_write(0x%x, 0x%x)\n", address
, value
));
559 if (!dmstatus
.authenticated
&& address
!= DMI_AUTHDATA
&&
560 address
!= DMI_DMCONTROL
)
563 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
564 unsigned i
= address
- DMI_DATA0
;
565 if (!abstractcs
.busy
)
566 write32(dmdata
, address
- DMI_DATA0
, value
);
568 if (abstractcs
.busy
&& abstractcs
.cmderr
== CMDERR_NONE
) {
569 abstractcs
.cmderr
= CMDERR_BUSY
;
572 if (!abstractcs
.busy
&& ((abstractauto
.autoexecdata
>> i
) & 1)) {
573 perform_abstract_command();
577 } else if (address
>= DMI_PROGBUF0
&& address
< DMI_PROGBUF0
+ progbufsize
) {
578 unsigned i
= address
- DMI_PROGBUF0
;
580 if (!abstractcs
.busy
)
581 write32(program_buffer
, i
, value
);
583 if (!abstractcs
.busy
&& ((abstractauto
.autoexecprogbuf
>> i
) & 1)) {
584 perform_abstract_command();
592 if (!dmcontrol
.dmactive
&& get_field(value
, DMI_DMCONTROL_DMACTIVE
))
594 dmcontrol
.dmactive
= get_field(value
, DMI_DMCONTROL_DMACTIVE
);
595 if (!dmstatus
.authenticated
)
597 if (dmcontrol
.dmactive
) {
598 dmcontrol
.haltreq
= get_field(value
, DMI_DMCONTROL_HALTREQ
);
599 dmcontrol
.resumereq
= get_field(value
, DMI_DMCONTROL_RESUMEREQ
);
600 dmcontrol
.hartreset
= get_field(value
, DMI_DMCONTROL_HARTRESET
);
601 dmcontrol
.ndmreset
= get_field(value
, DMI_DMCONTROL_NDMRESET
);
602 dmcontrol
.hartsel
= get_field(value
, ((1L<<hartsellen
)-1) <<
603 DMI_DMCONTROL_HARTSEL_OFFSET
);
605 processor_t
*proc
= current_proc();
607 proc
->halt_request
= dmcontrol
.haltreq
;
608 if (dmcontrol
.resumereq
) {
609 debug_rom_flags
[dmcontrol
.hartsel
] |= (1 << DEBUG_ROM_FLAG_RESUME
);
610 resumeack
[dmcontrol
.hartsel
] = false;
612 if (dmcontrol
.hartreset
) {
616 if (dmcontrol
.ndmreset
) {
617 for (size_t i
= 0; i
< sim
->nprocs(); i
++) {
618 proc
= sim
->get_core(i
);
627 return perform_abstract_command();
630 abstractcs
.cmderr
= (cmderr_t
) (((uint32_t) (abstractcs
.cmderr
)) & (~(uint32_t)(get_field(value
, DMI_ABSTRACTCS_CMDERR
))));
633 case DMI_ABSTRACTAUTO
:
634 abstractauto
.autoexecprogbuf
= get_field(value
,
635 DMI_ABSTRACTAUTO_AUTOEXECPROGBUF
);
636 abstractauto
.autoexecdata
= get_field(value
,
637 DMI_ABSTRACTAUTO_AUTOEXECDATA
);
640 sbcs
.readonaddr
= get_field(value
, DMI_SBCS_SBREADONADDR
);
641 sbcs
.sbaccess
= get_field(value
, DMI_SBCS_SBACCESS
);
642 sbcs
.autoincrement
= get_field(value
, DMI_SBCS_SBAUTOINCREMENT
);
643 sbcs
.readondata
= get_field(value
, DMI_SBCS_SBREADONDATA
);
644 sbcs
.error
&= ~get_field(value
, DMI_SBCS_SBERROR
);
647 sbaddress
[0] = value
;
648 if (sbcs
.error
== 0 && sbcs
.readonaddr
) {
653 sbaddress
[1] = value
;
656 sbaddress
[2] = value
;
659 sbaddress
[3] = value
;
663 if (sbcs
.error
== 0) {
665 if (sbcs
.autoincrement
&& sbcs
.error
== 0) {
680 D(fprintf(stderr
, "debug authentication: got 0x%x; 0x%x unlocks\n", value
,
681 challenge
+ secret
));
682 if (require_authentication
) {
683 if (value
== challenge
+ secret
) {
684 dmstatus
.authenticated
= true;
686 dmstatus
.authenticated
= false;
687 challenge
= random();