riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "mmu.h"
   5
   6 #include "debug_rom/debug_rom.h"
   7
   8 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
   9 {
  10   addr = DEBUG_START + addr;
  11
  12   if (addr >= DEBUG_RAM_START && addr + len <= DEBUG_RAM_END) {
  13     memcpy(bytes, debug_ram + addr - DEBUG_RAM_START, len);
  14     return true;
  15   }
  16
  17   if (addr >= DEBUG_ROM_START && addr + len <= DEBUG_ROM_END) {
  18     memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_START, len);
  19     return true;
  20   }
  21
  22   fprintf(stderr, "ERROR: invalid load from debug module: %ld bytes at 0x%lx\n",
  23       len, addr);
  24   return false;
  25 }
  26
  27 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
  28 {
  29   addr = DEBUG_START + addr;
  30
  31   if (addr & (len-1)) {
  32     fprintf(stderr, "ERROR: unaligned store to debug module: %ld bytes at 0x%lx\n",
  33         len, addr);
  34     return false;
  35   }
  36
  37   if (addr >= DEBUG_RAM_START && addr + len <= DEBUG_RAM_END) {
  38     memcpy(debug_ram + addr - DEBUG_RAM_START, bytes, len);
  39     return true;
  40   } else if (len == 4 && addr == DEBUG_CLEARDEBINT) {
  41     clear_interrupt(bytes[0] | (bytes[1] << 8) |
  42         (bytes[2] << 16) | (bytes[3] << 24));
  43     return true;
  44   } else if (len == 4 && addr == DEBUG_SETHALTNOT) {
  45     set_halt_notification(bytes[0] | (bytes[1] << 8) |
  46         (bytes[2] << 16) | (bytes[3] << 24));
  47     return true;
  48   }
  49
  50   fprintf(stderr, "ERROR: invalid store to debug module: %ld bytes at 0x%lx\n",
  51       len, addr);
  52   return false;
  53 }
  54
  55 void debug_module_t::ram_write32(unsigned int index, uint32_t value)
  56 {
  57   char* base = debug_ram + index * 4;
  58   base[0] = value & 0xff;
  59   base[1] = (value >> 8) & 0xff;
  60   base[2] = (value >> 16) & 0xff;
  61   base[3] = (value >> 24) & 0xff;
  62 }
  63
  64 uint32_t debug_module_t::ram_read32(unsigned int index)
  65 {
  66   // It'd be better for raw_page (and all memory) to be unsigned chars, but mem
  67   // in sim_t is just chars, so I'm following that convention.
  68   unsigned char* base = (unsigned char*) (debug_ram + index * 4);
  69   uint32_t value = ((uint32_t) base[0]) |
  70     (((uint32_t) base[1]) << 8) |
  71     (((uint32_t) base[2]) << 16) |
  72     (((uint32_t) base[3]) << 24);
  73   return value;
  74 }