riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "debug_defines.h"
   5 #include "opcodes.h"
   6 #include "mmu.h"
   7
   8 #include "debug_rom/debug_rom.h"
   9
  10 #if 1
  11 #  define D(x) x
  12 #else
  13 #  define D(x)
  14 #endif
  15
  16 ///////////////////////// debug_module_data_t
  17
  18 debug_module_data_t::debug_module_data_t()
  19 {
  20   memset(data, 0, sizeof(data));
  21 }
  22
  23 bool debug_module_data_t::load(reg_t addr, size_t len, uint8_t* bytes)
  24 {
  25   if (addr + len < sizeof(data)) {
  26     memcpy(bytes, data + addr, len);
  27     return true;
  28   }
  29
  30   fprintf(stderr, "ERROR: invalid load from debug_module_data_t: %zd bytes at 0x%016"
  31           PRIx64 "\n", len, addr);
  32
  33   return false;
  34 }
  35
  36 bool debug_module_data_t::store(reg_t addr, size_t len, const uint8_t* bytes)
  37 {
  38   D(fprintf(stderr, "debug_module_data_t store 0x%lx bytes at 0x%lx\n", len,
  39         addr));
  40
  41   if (addr + len < sizeof(data)) {
  42     memcpy(data + addr, bytes, len);
  43     return true;
  44   }
  45
  46   fprintf(stderr, "ERROR: invalid store to debug_module_data_t: %zd bytes at 0x%016"
  47           PRIx64 "\n", len, addr);
  48   return false;
  49 }
  50
  51 uint32_t debug_module_data_t::read32(reg_t addr) const
  52 {
  53   assert(addr + 4 <= sizeof(data));
  54   return data[addr] |
  55     (data[addr + 1] << 8) |
  56     (data[addr + 2] << 16) |
  57     (data[addr + 3] << 24);
  58 }
  59
  60 void debug_module_data_t::write32(reg_t addr, uint32_t value)
  61 {
  62   fprintf(stderr, "debug_module_data_t::write32(0x%lx, 0x%x)\n", addr, value);
  63   assert(addr + 4 <= sizeof(data));
  64   data[addr] = value & 0xff;
  65   data[addr + 1] = (value >> 8) & 0xff;
  66   data[addr + 2] = (value >> 16) & 0xff;
  67   data[addr + 3] = (value >> 24) & 0xff;
  68 }
  69
  70 ///////////////////////// debug_module_t
  71
  72 debug_module_t::debug_module_t(sim_t *sim) : sim(sim),
  73   next_action(jal(ZERO, 0)),
  74   action_executed(false)
  75 {
  76   dmcontrol = {0};
  77   dmcontrol.version = 1;
  78
  79   for (unsigned i = 0; i < DEBUG_ROM_ENTRY_SIZE / 4; i++) {
  80     write32(debug_rom_entry, i, jal(ZERO, 0));
  81     halted[i] = false;
  82   }
  83
  84   memset(program_buffer, 0, sizeof(program_buffer));
  85 }
  86
  87 void debug_module_t::reset()
  88 {
  89   for (unsigned i = 0; i < sim->nprocs(); i++) {
  90     processor_t *proc = sim->get_core(i);
  91     if (proc)
  92       proc->halt_request = false;
  93   }
  94
  95   dmcontrol = {0};
  96   dmcontrol.authenticated = 1;
  97   dmcontrol.version = 1;
  98   dmcontrol.authtype = dmcontrol.AUTHTYPE_NOAUTH;
  99
 100   abstractcs = {0};
 101   abstractcs.datacount = sizeof(dmdata.data) / 4;
 102 }
 103
 104 void debug_module_t::add_device(bus_t *bus) {
 105   bus->add_device(DEBUG_START, this);
 106   bus->add_device(DEBUG_EXCHANGE, &dmdata);
 107 }
 108
 109 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
 110 {
 111   addr = DEBUG_START + addr;
 112
 113   if (addr >= DEBUG_ROM_ENTRY &&
 114       addr < DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE) {
 115
 116     if (read32(debug_rom_entry, dmcontrol.hartsel) == jal(ZERO, 0)) {
 117       // We're here in an infinite loop. That means that whatever abstract
 118       // command has complete.
 119       abstractcs.busy = false;
 120     }
 121
 122     action_executed = true;
 123
 124     halted[(addr - DEBUG_ROM_ENTRY) / 4] = true;
 125     memcpy(bytes, debug_rom_entry + addr - DEBUG_ROM_ENTRY, len);
 126     return true;
 127   }
 128
 129   if (action_executed) {
 130     // Restore the jump-to-self loop.
 131     write32(debug_rom_entry, dmcontrol.hartsel, next_action);
 132     next_action = jal(ZERO, 0);
 133     action_executed = false;
 134   }
 135
 136   if (addr >= DEBUG_ROM_CODE &&
 137       addr < DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE) {
 138
 139     if (read32(debug_rom_code, 0) == dret()) {
 140       abstractcs.busy = false;
 141       halted[dmcontrol.hartsel] = false;
 142     }
 143
 144     memcpy(bytes, debug_rom_code + addr - DEBUG_ROM_CODE, len);
 145     return true;
 146   }
 147
 148   if (addr >= DEBUG_RAM_START && addr < DEBUG_RAM_END) {
 149     memcpy(bytes, program_buffer + addr - DEBUG_RAM_START, len);
 150     return true;
 151   }
 152
 153   if (addr >= DEBUG_ROM_EXCEPTION &&
 154       addr < DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE) {
 155     memcpy(bytes, debug_rom_exception + addr - DEBUG_ROM_EXCEPTION, len);
 156     if (abstractcs.cmderr == abstractcs.CMDERR_NONE) {
 157       abstractcs.cmderr = abstractcs.CMDERR_EXCEPTION;
 158     }
 159     return true;
 160   }
 161
 162   fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
 163           PRIx64 "\n", len, addr);
 164
 165   return false;
 166 }
 167
 168 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 169 {
 170   addr = DEBUG_START + addr;
 171
 172   if (addr >= DEBUG_RAM_START && addr < DEBUG_RAM_END) {
 173     memcpy(program_buffer + addr - DEBUG_RAM_START, bytes, len);
 174     return true;
 175   }
 176
 177   fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
 178           PRIx64 "\n", len, addr);
 179   return false;
 180 }
 181
 182 void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value)
 183 {
 184   uint8_t* base = memory + index * 4;
 185   base[0] = value & 0xff;
 186   base[1] = (value >> 8) & 0xff;
 187   base[2] = (value >> 16) & 0xff;
 188   base[3] = (value >> 24) & 0xff;
 189 }
 190
 191 uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index)
 192 {
 193   uint8_t* base = memory + index * 4;
 194   uint32_t value = ((uint32_t) base[0]) |
 195     (((uint32_t) base[1]) << 8) |
 196     (((uint32_t) base[2]) << 16) |
 197     (((uint32_t) base[3]) << 24);
 198   return value;
 199 }
 200
 201 processor_t *debug_module_t::current_proc() const
 202 {
 203   processor_t *proc = NULL;
 204   try {
 205     proc = sim->get_core(dmcontrol.hartsel);
 206   } catch (const std::out_of_range&) {
 207   }
 208   return proc;
 209 }
 210
 211 bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 212 {
 213   uint32_t result = 0;
 214   D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
 215   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 216     unsigned i = address - DMI_DATA0;
 217     result = dmdata.read32(4 * i);
 218
 219     if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
 220       abstractcs.cmderr = abstractcs.CMDERR_BUSY;
 221     }
 222
 223     bool autoexec = false;
 224     switch (i) {
 225       case 0:   autoexec = abstractcs.autoexec0; break;
 226       case 1:   autoexec = abstractcs.autoexec1; break;
 227       case 2:   autoexec = abstractcs.autoexec2; break;
 228       case 3:   autoexec = abstractcs.autoexec3; break;
 229       case 4:   autoexec = abstractcs.autoexec4; break;
 230       case 5:   autoexec = abstractcs.autoexec5; break;
 231       case 6:   autoexec = abstractcs.autoexec6; break;
 232       case 7:   autoexec = abstractcs.autoexec7; break;
 233     }
 234     if (autoexec) {
 235       perform_abstract_command();
 236     }
 237   } else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) {
 238     result = read32(program_buffer, address - DMI_IBUF0);
 239   } else {
 240     switch (address) {
 241       case DMI_DMCONTROL:
 242         {
 243           processor_t *proc = current_proc();
 244           if (proc) {
 245             if (halted[dmcontrol.hartsel]) {
 246               dmcontrol.hartstatus = dmcontrol.HARTSTATUS_HALTED;
 247             } else {
 248               dmcontrol.hartstatus = dmcontrol.HARTSTATUS_RUNNING;
 249             }
 250             dmcontrol.haltreq = proc->halt_request;
 251           } else {
 252             dmcontrol.hartstatus = dmcontrol.HARTSTATUS_NOTEXIST;
 253           }
 254           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
 255           result = set_field(result, DMI_DMCONTROL_RESET, dmcontrol.reset);
 256           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
 257           result = set_field(result, DMI_DMCONTROL_HARTSTATUS, dmcontrol.hartstatus);
 258           result = set_field(result, DMI_DMCONTROL_HARTSEL, dmcontrol.hartsel);
 259           result = set_field(result, DMI_DMCONTROL_AUTHENTICATED, dmcontrol.authenticated);
 260           result = set_field(result, DMI_DMCONTROL_AUTHBUSY, dmcontrol.authbusy);
 261           result = set_field(result, DMI_DMCONTROL_AUTHTYPE, dmcontrol.authtype);
 262           result = set_field(result, DMI_DMCONTROL_VERSION, dmcontrol.version);
 263         }
 264         break;
 265       case DMI_ABSTRACTCS:
 266         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC7, abstractcs.autoexec7);
 267         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC6, abstractcs.autoexec6);
 268         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC5, abstractcs.autoexec5);
 269         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC4, abstractcs.autoexec4);
 270         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC3, abstractcs.autoexec3);
 271         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC2, abstractcs.autoexec2);
 272         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC1, abstractcs.autoexec1);
 273         result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC0, abstractcs.autoexec0);
 274         result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr);
 275         result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy);
 276         result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount);
 277         break;
 278       case DMI_ACCESSCS:
 279         result = progsize << DMI_ACCESSCS_PROGSIZE_OFFSET;
 280         break;
 281       case DMI_COMMAND:
 282         result = 0;
 283         break;
 284       default:
 285         D(fprintf(stderr, "error\n"));
 286         return false;
 287     }
 288   }
 289   D(fprintf(stderr, "0x%x\n", result));
 290   *value = result;
 291   return true;
 292 }
 293
 294 bool debug_module_t::perform_abstract_command()
 295 {
 296   if (abstractcs.cmderr != abstractcs.CMDERR_NONE)
 297     return true;
 298   if (abstractcs.busy) {
 299     abstractcs.cmderr = abstractcs.CMDERR_BUSY;
 300     return true;
 301   }
 302
 303   if ((command >> 24) == 0) {
 304     // register access
 305     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
 306     bool write = get_field(command, AC_ACCESS_REGISTER_WRITE);
 307     unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO);
 308
 309     if (regno < 0x1000 || regno >= 0x1020) {
 310       abstractcs.cmderr = abstractcs.CMDERR_NOTSUP;
 311       return true;
 312     }
 313
 314     unsigned regnum = regno - 0x1000;
 315
 316     if (!halted[dmcontrol.hartsel]) {
 317       abstractcs.cmderr = abstractcs.CMDERR_HALTRESUME;
 318       return true;
 319     }
 320
 321     switch (size) {
 322       case 2:
 323         if (write)
 324           write32(debug_rom_code, 0, lw(regnum, ZERO, DEBUG_EXCHANGE));
 325         else
 326           write32(debug_rom_code, 0, sw(regnum, ZERO, DEBUG_EXCHANGE));
 327         break;
 328       case 3:
 329         if (write)
 330           write32(debug_rom_code, 0, ld(regnum, ZERO, DEBUG_EXCHANGE));
 331         else
 332           write32(debug_rom_code, 0, sd(regnum, ZERO, DEBUG_EXCHANGE));
 333         break;
 334       /*
 335       case 4:
 336         if (write)
 337           write32(debug_rom_code, 0, lq(regnum, ZERO, DEBUG_EXCHANGE));
 338         else
 339           write32(debug_rom_code, 0, sq(regnum, ZERO, DEBUG_EXCHANGE));
 340         break;
 341         */
 342       default:
 343         abstractcs.cmderr = abstractcs.CMDERR_NOTSUP;
 344         return true;
 345     }
 346     if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
 347       write32(debug_rom_code, 1, jal(ZERO, DEBUG_RAM_START - DEBUG_ROM_CODE - 4));
 348     } else {
 349       write32(debug_rom_code, 1, ebreak());
 350     }
 351
 352     if (get_field(command, AC_ACCESS_REGISTER_PREEXEC)) {
 353       write32(debug_rom_entry, dmcontrol.hartsel,
 354           jal(ZERO, DEBUG_RAM_START - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
 355       next_action =
 356         jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel));
 357     } else {
 358       write32(debug_rom_entry, dmcontrol.hartsel,
 359           jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
 360     }
 361
 362     write32(debug_rom_exception, dmcontrol.hartsel,
 363         jal(ZERO, (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel) - DEBUG_ROM_EXCEPTION));
 364     abstractcs.busy = true;
 365   } else {
 366     abstractcs.cmderr = abstractcs.CMDERR_NOTSUP;
 367   }
 368   return true;
 369 }
 370
 371 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 372 {
 373   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
 374   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 375     unsigned i = address - DMI_DATA0;
 376     dmdata.write32(4 * i, value);
 377
 378     if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
 379       abstractcs.cmderr = abstractcs.CMDERR_BUSY;
 380     }
 381
 382     bool autoexec = false;
 383     switch (i) {
 384       case 0:   autoexec = abstractcs.autoexec0; break;
 385       case 1:   autoexec = abstractcs.autoexec1; break;
 386       case 2:   autoexec = abstractcs.autoexec2; break;
 387       case 3:   autoexec = abstractcs.autoexec3; break;
 388       case 4:   autoexec = abstractcs.autoexec4; break;
 389       case 5:   autoexec = abstractcs.autoexec5; break;
 390       case 6:   autoexec = abstractcs.autoexec6; break;
 391       case 7:   autoexec = abstractcs.autoexec7; break;
 392     }
 393     if (autoexec) {
 394       perform_abstract_command();
 395     }
 396     return true;
 397
 398   } else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) {
 399     write32(program_buffer, address - DMI_IBUF0, value);
 400     return true;
 401   } else {
 402     switch (address) {
 403       case DMI_DMCONTROL:
 404         {
 405           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
 406           if (dmcontrol.dmactive) {
 407             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
 408             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
 409             dmcontrol.reset = get_field(value, DMI_DMCONTROL_RESET);
 410             dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
 411           } else {
 412             reset();
 413           }
 414           processor_t *proc = current_proc();
 415           if (proc) {
 416             proc->halt_request = dmcontrol.haltreq;
 417             if (dmcontrol.resumereq) {
 418               write32(debug_rom_code, 0, dret());
 419               write32(debug_rom_entry, dmcontrol.hartsel,
 420                   jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
 421               abstractcs.busy = true;
 422             }
 423           }
 424         }
 425         return true;
 426
 427       case DMI_COMMAND:
 428         command = value;
 429         return perform_abstract_command();
 430
 431       case DMI_ABSTRACTCS:
 432         abstractcs.autoexec7 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC7);
 433         abstractcs.autoexec6 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC6);
 434         abstractcs.autoexec5 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC5);
 435         abstractcs.autoexec4 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC4);
 436         abstractcs.autoexec3 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC3);
 437         abstractcs.autoexec2 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC2);
 438         abstractcs.autoexec1 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC1);
 439         abstractcs.autoexec0 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC0);
 440         if (get_field(value, DMI_ABSTRACTCS_CMDERR) == abstractcs.CMDERR_NONE) {
 441           abstractcs.cmderr = abstractcs.CMDERR_NONE;
 442         }
 443         return true;
 444     }
 445   }
 446   return false;
 447 }