riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "debug_defines.h"
   5 #include "opcodes.h"
   6 #include "mmu.h"
   7
   8 #include "debug_rom/debug_rom.h"
   9 #include "debug_rom_defines.h"
  10
  11 #if 0
  12 #  define D(x) x
  13 #else
  14 #  define D(x)
  15 #endif
  16
  17 ///////////////////////// debug_module_t
  18
  19 debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
  20     bool require_authentication) :
  21   progbufsize(progbufsize),
  22   program_buffer_bytes(4 + 4*progbufsize),
  23   max_bus_master_bits(max_bus_master_bits),
  24   require_authentication(require_authentication),
  25   debug_progbuf_start(debug_data_start - program_buffer_bytes),
  26   debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
  27   sim(sim)
  28 {
  29   D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
  30   D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));
  31   D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start));
  32
  33   program_buffer = new uint8_t[program_buffer_bytes];
  34
  35   memset(halted, 0, sizeof(halted));
  36   memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
  37   memset(resumeack, 0, sizeof(resumeack));
  38   memset(havereset, 0, sizeof(havereset));
  39   memset(program_buffer, 0, program_buffer_bytes);
  40   program_buffer[4*progbufsize] = ebreak();
  41   program_buffer[4*progbufsize+1] = ebreak() >> 8;
  42   program_buffer[4*progbufsize+2] = ebreak() >> 16;
  43   program_buffer[4*progbufsize+3] = ebreak() >> 24;
  44   memset(dmdata, 0, sizeof(dmdata));
  45
  46   write32(debug_rom_whereto, 0,
  47           jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO));
  48
  49   memset(debug_abstract, 0, sizeof(debug_abstract));
  50
  51   reset();
  52 }
  53
  54 debug_module_t::~debug_module_t()
  55 {
  56   delete[] program_buffer;
  57 }
  58
  59 void debug_module_t::reset()
  60 {
  61   for (unsigned i = 0; i < sim->nprocs(); i++) {
  62     processor_t *proc = sim->get_core(i);
  63     if (proc)
  64       proc->halt_request = false;
  65   }
  66
  67   dmcontrol = {0};
  68
  69   dmstatus = {0};
  70   dmstatus.impebreak = true;
  71   dmstatus.authenticated = !require_authentication;
  72   dmstatus.version = 2;
  73
  74   abstractcs = {0};
  75   abstractcs.datacount = sizeof(dmdata) / 4;
  76   abstractcs.progbufsize = progbufsize;
  77
  78   abstractauto = {0};
  79
  80   sbcs = {0};
  81   if (max_bus_master_bits > 0) {
  82     sbcs.version = 1;
  83     sbcs.asize = sizeof(reg_t) * 8;
  84   }
  85   if (max_bus_master_bits >= 64)
  86     sbcs.access64 = true;
  87   if (max_bus_master_bits >= 32)
  88     sbcs.access32 = true;
  89   if (max_bus_master_bits >= 16)
  90     sbcs.access16 = true;
  91   if (max_bus_master_bits >= 8)
  92     sbcs.access8 = true;
  93
  94   challenge = random();
  95 }
  96
  97 void debug_module_t::add_device(bus_t *bus) {
  98   bus->add_device(DEBUG_START, this);
  99 }
 100
 101 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
 102 {
 103   addr = DEBUG_START + addr;
 104
 105   if (addr >= DEBUG_ROM_ENTRY &&
 106       (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) {
 107     memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len);
 108     return true;
 109   }
 110
 111   if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) {
 112     memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len);
 113     return true;
 114   }
 115
 116   if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) {
 117     memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len);
 118     return true;
 119   }
 120
 121   if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) {
 122     memcpy(bytes, debug_abstract + addr - debug_abstract_start, len);
 123     return true;
 124   }
 125
 126   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 127     memcpy(bytes, dmdata + addr - debug_data_start, len);
 128     return true;
 129   }
 130
 131   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) {
 132     memcpy(bytes, program_buffer + addr - debug_progbuf_start, len);
 133     return true;
 134   }
 135
 136   fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
 137           PRIx64 "\n", len, addr);
 138
 139   return false;
 140 }
 141
 142 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 143 {
 144   D(
 145       switch (len) {
 146         case 4:
 147           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); "
 148               "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes,
 149               dmcontrol.hartsel);
 150           break;
 151         default:
 152           fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); "
 153               "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel);
 154           break;
 155       }
 156    );
 157
 158   uint8_t id_bytes[4];
 159   uint32_t id = 0;
 160   if (len == 4) {
 161     memcpy(id_bytes, bytes, 4);
 162     id = read32(id_bytes, 0);
 163   }
 164
 165   addr = DEBUG_START + addr;
 166
 167   if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
 168     memcpy(dmdata + addr - debug_data_start, bytes, len);
 169     return true;
 170   }
 171
 172   if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) {
 173     memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
 174
 175     return true;
 176   }
 177
 178   if (addr == DEBUG_ROM_HALTED) {
 179     assert (len == 4);
 180     halted[id] = true;
 181     if (dmcontrol.hartsel == id) {
 182         if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){
 183           if (dmcontrol.hartsel == id) {
 184               abstractcs.busy = false;
 185           }
 186         }
 187     }
 188     return true;
 189   }
 190
 191   if (addr == DEBUG_ROM_GOING) {
 192     debug_rom_flags[dmcontrol.hartsel] &= ~(1 << DEBUG_ROM_FLAG_GO);
 193     return true;
 194   }
 195
 196   if (addr == DEBUG_ROM_RESUMING) {
 197     assert (len == 4);
 198     halted[id] = false;
 199     resumeack[id] = true;
 200     debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME);
 201     return true;
 202   }
 203
 204   if (addr == DEBUG_ROM_EXCEPTION) {
 205     if (abstractcs.cmderr == CMDERR_NONE) {
 206       abstractcs.cmderr = CMDERR_EXCEPTION;
 207     }
 208     return true;
 209   }
 210
 211   fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
 212           PRIx64 "\n", len, addr);
 213   return false;
 214 }
 215
 216 void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value)
 217 {
 218   uint8_t* base = memory + index * 4;
 219   base[0] = value & 0xff;
 220   base[1] = (value >> 8) & 0xff;
 221   base[2] = (value >> 16) & 0xff;
 222   base[3] = (value >> 24) & 0xff;
 223 }
 224
 225 uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index)
 226 {
 227   uint8_t* base = memory + index * 4;
 228   uint32_t value = ((uint32_t) base[0]) |
 229     (((uint32_t) base[1]) << 8) |
 230     (((uint32_t) base[2]) << 16) |
 231     (((uint32_t) base[3]) << 24);
 232   return value;
 233 }
 234
 235 processor_t *debug_module_t::current_proc() const
 236 {
 237   processor_t *proc = NULL;
 238   try {
 239     proc = sim->get_core(dmcontrol.hartsel);
 240   } catch (const std::out_of_range&) {
 241   }
 242   return proc;
 243 }
 244
 245 unsigned debug_module_t::sb_access_bits()
 246 {
 247   return 8 << sbcs.sbaccess;
 248 }
 249
 250 void debug_module_t::sb_autoincrement()
 251 {
 252   if (!sbcs.autoincrement || !max_bus_master_bits)
 253     return;
 254
 255   uint64_t value = sbaddress[0] + sb_access_bits() / 8;
 256   sbaddress[0] = value;
 257   uint32_t carry = value >> 32;
 258
 259   value = sbaddress[1] + carry;
 260   sbaddress[1] = value;
 261   carry = value >> 32;
 262
 263   value = sbaddress[2] + carry;
 264   sbaddress[2] = value;
 265   carry = value >> 32;
 266
 267   sbaddress[3] += carry;
 268 }
 269
 270 void debug_module_t::sb_read()
 271 {
 272   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
 273   try {
 274     if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
 275       sbdata[0] = sim->debug_mmu->load_uint8(address);
 276     } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
 277       sbdata[0] = sim->debug_mmu->load_uint16(address);
 278     } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
 279       sbdata[0] = sim->debug_mmu->load_uint32(address);
 280     } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
 281       uint64_t value = sim->debug_mmu->load_uint32(address);
 282       sbdata[0] = value;
 283       sbdata[1] = value >> 32;
 284     } else {
 285       sbcs.error = 3;
 286     }
 287   } catch (trap_load_access_fault& t) {
 288     sbcs.error = 2;
 289   }
 290 }
 291
 292 void debug_module_t::sb_write()
 293 {
 294   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
 295   D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
 296   if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
 297     sim->debug_mmu->store_uint8(address, sbdata[0]);
 298   } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
 299     sim->debug_mmu->store_uint16(address, sbdata[0]);
 300   } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
 301     sim->debug_mmu->store_uint32(address, sbdata[0]);
 302   } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
 303     sim->debug_mmu->store_uint64(address,
 304         (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
 305   } else {
 306     sbcs.error = 3;
 307   }
 308 }
 309
 310 bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 311 {
 312   uint32_t result = 0;
 313   D(fprintf(stderr, "dmi_read(0x%x) -> ", address));
 314   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 315     unsigned i = address - DMI_DATA0;
 316     result = read32(dmdata, i);
 317     if (abstractcs.busy) {
 318       result = -1;
 319       fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 320     }
 321
 322     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 323       abstractcs.cmderr = CMDERR_BUSY;
 324     }
 325
 326     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 327       perform_abstract_command();
 328     }
 329   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) {
 330     unsigned i = address - DMI_PROGBUF0;
 331     result = read32(program_buffer, i);
 332     if (abstractcs.busy) {
 333       result = -1;
 334       fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i);
 335     }
 336     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 337       perform_abstract_command();
 338     }
 339
 340   } else {
 341     switch (address) {
 342       case DMI_DMCONTROL:
 343         {
 344           processor_t *proc = current_proc();
 345           if (proc)
 346             dmcontrol.haltreq = proc->halt_request;
 347
 348           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
 349           result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
 350           result = set_field(result, ((1L<<hartsellen)-1) <<
 351               DMI_DMCONTROL_HARTSEL_OFFSET, dmcontrol.hartsel);
 352           result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
 353           result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
 354           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
 355         }
 356         break;
 357       case DMI_DMSTATUS:
 358         {
 359           processor_t *proc = current_proc();
 360
 361           dmstatus.allnonexistant = false;
 362           dmstatus.allunavail = false;
 363           dmstatus.allrunning = false;
 364           dmstatus.allhalted = false;
 365           dmstatus.allresumeack = false;
 366           if (proc) {
 367             if (halted[dmcontrol.hartsel]) {
 368               dmstatus.allhalted = true;
 369             } else {
 370               dmstatus.allrunning = true;
 371             }
 372           } else {
 373             dmstatus.allnonexistant = true;
 374           }
 375           dmstatus.anynonexistant = dmstatus.allnonexistant;
 376           dmstatus.anyunavail = dmstatus.allunavail;
 377           dmstatus.anyrunning = dmstatus.allrunning;
 378           dmstatus.anyhalted = dmstatus.allhalted;
 379           if (proc) {
 380             if (resumeack[dmcontrol.hartsel]) {
 381               dmstatus.allresumeack = true;
 382             } else {
 383               dmstatus.allresumeack = false;
 384             }
 385           } else {
 386             dmstatus.allresumeack = false;
 387           }
 388
 389           result = set_field(result, DMI_DMSTATUS_IMPEBREAK,
 390               dmstatus.impebreak);
 391           result = set_field(result, DMI_DMSTATUS_ALLHAVERESET,
 392               havereset[dmcontrol.hartsel]);
 393           result = set_field(result, DMI_DMSTATUS_ANYHAVERESET,
 394               havereset[dmcontrol.hartsel]);
 395           result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
 396           result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
 397           result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
 398           result = set_field(result, DMI_DMSTATUS_ALLHALTED, dmstatus.allhalted);
 399           result = set_field(result, DMI_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack);
 400           result = set_field(result, DMI_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant);
 401           result = set_field(result, DMI_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail);
 402           result = set_field(result, DMI_DMSTATUS_ANYRUNNING, dmstatus.anyrunning);
 403           result = set_field(result, DMI_DMSTATUS_ANYHALTED, dmstatus.anyhalted);
 404           result = set_field(result, DMI_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack);
 405           result = set_field(result, DMI_DMSTATUS_AUTHENTICATED, dmstatus.authenticated);
 406           result = set_field(result, DMI_DMSTATUS_AUTHBUSY, dmstatus.authbusy);
 407           result = set_field(result, DMI_DMSTATUS_VERSION, dmstatus.version);
 408         }
 409         break;
 410       case DMI_ABSTRACTCS:
 411         result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr);
 412         result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy);
 413         result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount);
 414         result = set_field(result, DMI_ABSTRACTCS_PROGBUFSIZE,
 415             abstractcs.progbufsize);
 416         break;
 417       case DMI_ABSTRACTAUTO:
 418         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf);
 419         result = set_field(result, DMI_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata);
 420         break;
 421       case DMI_COMMAND:
 422         result = 0;
 423         break;
 424       case DMI_HARTINFO:
 425         result = set_field(result, DMI_HARTINFO_NSCRATCH, 1);
 426         result = set_field(result, DMI_HARTINFO_DATAACCESS, 1);
 427         result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount);
 428         result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start);
 429         break;
 430       case DMI_SBCS:
 431         result = set_field(result, DMI_SBCS_SBVERSION, sbcs.version);
 432         result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr);
 433         result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess);
 434         result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement);
 435         result = set_field(result, DMI_SBCS_SBREADONDATA, sbcs.readondata);
 436         result = set_field(result, DMI_SBCS_SBERROR, sbcs.error);
 437         result = set_field(result, DMI_SBCS_SBASIZE, sbcs.asize);
 438         result = set_field(result, DMI_SBCS_SBACCESS128, sbcs.access128);
 439         result = set_field(result, DMI_SBCS_SBACCESS64, sbcs.access64);
 440         result = set_field(result, DMI_SBCS_SBACCESS32, sbcs.access32);
 441         result = set_field(result, DMI_SBCS_SBACCESS16, sbcs.access16);
 442         result = set_field(result, DMI_SBCS_SBACCESS8, sbcs.access8);
 443         break;
 444       case DMI_SBADDRESS0:
 445         result = sbaddress[0];
 446         break;
 447       case DMI_SBADDRESS1:
 448         result = sbaddress[1];
 449         break;
 450       case DMI_SBADDRESS2:
 451         result = sbaddress[2];
 452         break;
 453       case DMI_SBADDRESS3:
 454         result = sbaddress[3];
 455         break;
 456       case DMI_SBDATA0:
 457         result = sbdata[0];
 458         if (sbcs.error == 0) {
 459           sb_autoincrement();
 460           if (sbcs.readondata) {
 461             sb_read();
 462           }
 463         }
 464         break;
 465       case DMI_SBDATA1:
 466         result = sbdata[1];
 467         break;
 468       case DMI_SBDATA2:
 469         result = sbdata[2];
 470         break;
 471       case DMI_SBDATA3:
 472         result = sbdata[3];
 473         break;
 474       case DMI_AUTHDATA:
 475         result = challenge;
 476         break;
 477       default:
 478         result = 0;
 479         D(fprintf(stderr, "Unexpected. Returning Error."));
 480         return false;
 481     }
 482   }
 483   D(fprintf(stderr, "0x%x\n", result));
 484   *value = result;
 485   return true;
 486 }
 487
 488 bool debug_module_t::perform_abstract_command()
 489 {
 490   if (abstractcs.cmderr != CMDERR_NONE)
 491     return true;
 492   if (abstractcs.busy) {
 493     abstractcs.cmderr = CMDERR_BUSY;
 494     return true;
 495   }
 496
 497   if ((command >> 24) == 0) {
 498     // register access
 499     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
 500     bool write = get_field(command, AC_ACCESS_REGISTER_WRITE);
 501     unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO);
 502
 503     if (!halted[dmcontrol.hartsel]) {
 504       abstractcs.cmderr = CMDERR_HALTRESUME;
 505       return true;
 506     }
 507
 508     unsigned i = 0;
 509     if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
 510
 511       if (regno < 0x1000 && progbufsize < 2) {
 512         // Make the debugger use the program buffer if it's available, so it
 513         // can test both use cases.
 514         write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH));
 515
 516         if (write) {
 517           switch (size) {
 518             case 2:
 519               write32(debug_abstract, i++, lw(S0, ZERO, debug_data_start));
 520               break;
 521             case 3:
 522               write32(debug_abstract, i++, ld(S0, ZERO, debug_data_start));
 523               break;
 524             default:
 525               abstractcs.cmderr = CMDERR_NOTSUP;
 526               return true;
 527           }
 528           write32(debug_abstract, i++, csrw(S0, regno));
 529
 530         } else {
 531           write32(debug_abstract, i++, csrr(S0, regno));
 532           switch (size) {
 533             case 2:
 534               write32(debug_abstract, i++, sw(S0, ZERO, debug_data_start));
 535               break;
 536             case 3:
 537               write32(debug_abstract, i++, sd(S0, ZERO, debug_data_start));
 538               break;
 539             default:
 540               abstractcs.cmderr = CMDERR_NOTSUP;
 541               return true;
 542           }
 543         }
 544         write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH));
 545
 546       } else if (regno >= 0x1000 && regno < 0x1020) {
 547         unsigned regnum = regno - 0x1000;
 548
 549         switch (size) {
 550           case 2:
 551             if (write)
 552               write32(debug_abstract, i++, lw(regnum, ZERO, debug_data_start));
 553             else
 554               write32(debug_abstract, i++, sw(regnum, ZERO, debug_data_start));
 555             break;
 556           case 3:
 557             if (write)
 558               write32(debug_abstract, i++, ld(regnum, ZERO, debug_data_start));
 559             else
 560               write32(debug_abstract, i++, sd(regnum, ZERO, debug_data_start));
 561             break;
 562           default:
 563             abstractcs.cmderr = CMDERR_NOTSUP;
 564             return true;
 565         }
 566
 567       } else if (regno >= 0x1020 && regno < 0x1040) {
 568         // Don't force the debugger to use progbuf if it exists, so the
 569         // debugger has to make the decision not to use abstract commands to
 570         // access 64-bit FPRs on 32-bit targets.
 571         unsigned fprnum = regno - 0x1020;
 572
 573         if (write) {
 574           switch (size) {
 575             case 2:
 576               write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start));
 577               break;
 578             case 3:
 579               write32(debug_abstract, i++, fld(fprnum, ZERO, debug_data_start));
 580               break;
 581             default:
 582               abstractcs.cmderr = CMDERR_NOTSUP;
 583               return true;
 584           }
 585
 586         } else {
 587           switch (size) {
 588             case 2:
 589               write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start));
 590               break;
 591             case 3:
 592               write32(debug_abstract, i++, fsd(fprnum, ZERO, debug_data_start));
 593               break;
 594             default:
 595               abstractcs.cmderr = CMDERR_NOTSUP;
 596               return true;
 597           }
 598         }
 599
 600       } else {
 601         abstractcs.cmderr = CMDERR_NOTSUP;
 602         return true;
 603       }
 604     }
 605
 606     if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
 607       write32(debug_abstract, i,
 608           jal(ZERO, debug_progbuf_start - debug_abstract_start - 4 * i));
 609       i++;
 610     } else {
 611       write32(debug_abstract, i++, ebreak());
 612     }
 613
 614     debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
 615
 616     abstractcs.busy = true;
 617   } else {
 618     abstractcs.cmderr = CMDERR_NOTSUP;
 619   }
 620   return true;
 621 }
 622
 623 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 624 {
 625   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
 626
 627   if (!dmstatus.authenticated && address != DMI_AUTHDATA &&
 628       address != DMI_DMCONTROL)
 629     return false;
 630
 631   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
 632     unsigned i = address - DMI_DATA0;
 633     if (!abstractcs.busy)
 634       write32(dmdata, address - DMI_DATA0, value);
 635
 636     if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) {
 637       abstractcs.cmderr = CMDERR_BUSY;
 638     }
 639
 640     if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) {
 641       perform_abstract_command();
 642     }
 643     return true;
 644
 645   } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progbufsize) {
 646     unsigned i = address - DMI_PROGBUF0;
 647
 648     if (!abstractcs.busy)
 649       write32(program_buffer, i, value);
 650
 651     if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) {
 652       perform_abstract_command();
 653     }
 654     return true;
 655
 656   } else {
 657     switch (address) {
 658       case DMI_DMCONTROL:
 659         {
 660           if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE))
 661             reset();
 662           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
 663           if (!dmstatus.authenticated)
 664             return true;
 665           if (dmcontrol.dmactive) {
 666             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
 667             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
 668             dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET);
 669             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
 670             dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) <<
 671                 DMI_DMCONTROL_HARTSEL_OFFSET);
 672             if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) {
 673               havereset[dmcontrol.hartsel] = false;
 674             }
 675           }
 676           processor_t *proc = current_proc();
 677           if (proc) {
 678             proc->halt_request = dmcontrol.haltreq;
 679             if (dmcontrol.resumereq) {
 680               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
 681               resumeack[dmcontrol.hartsel] = false;
 682             }
 683             if (dmcontrol.hartreset) {
 684               proc->reset();
 685             }
 686           }
 687           if (dmcontrol.ndmreset) {
 688             for (size_t i = 0; i < sim->nprocs(); i++) {
 689               proc = sim->get_core(i);
 690               proc->reset();
 691             }
 692           }
 693         }
 694         return true;
 695
 696       case DMI_COMMAND:
 697         command = value;
 698         return perform_abstract_command();
 699
 700       case DMI_ABSTRACTCS:
 701         abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DMI_ABSTRACTCS_CMDERR))));
 702         return true;
 703
 704       case DMI_ABSTRACTAUTO:
 705         abstractauto.autoexecprogbuf = get_field(value,
 706             DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
 707         abstractauto.autoexecdata = get_field(value,
 708             DMI_ABSTRACTAUTO_AUTOEXECDATA);
 709         return true;
 710       case DMI_SBCS:
 711         sbcs.readonaddr = get_field(value, DMI_SBCS_SBREADONADDR);
 712         sbcs.sbaccess = get_field(value, DMI_SBCS_SBACCESS);
 713         sbcs.autoincrement = get_field(value, DMI_SBCS_SBAUTOINCREMENT);
 714         sbcs.readondata = get_field(value, DMI_SBCS_SBREADONDATA);
 715         sbcs.error &= ~get_field(value, DMI_SBCS_SBERROR);
 716         return true;
 717       case DMI_SBADDRESS0:
 718         sbaddress[0] = value;
 719         if (sbcs.error == 0 && sbcs.readonaddr) {
 720           sb_read();
 721         }
 722         return true;
 723       case DMI_SBADDRESS1:
 724         sbaddress[1] = value;
 725         return true;
 726       case DMI_SBADDRESS2:
 727         sbaddress[2] = value;
 728         return true;
 729       case DMI_SBADDRESS3:
 730         sbaddress[3] = value;
 731         return true;
 732       case DMI_SBDATA0:
 733         sbdata[0] = value;
 734         if (sbcs.error == 0) {
 735           sb_write();
 736           if (sbcs.autoincrement && sbcs.error == 0) {
 737             sb_autoincrement();
 738           }
 739         }
 740         return true;
 741       case DMI_SBDATA1:
 742         sbdata[1] = value;
 743         return true;
 744       case DMI_SBDATA2:
 745         sbdata[2] = value;
 746         return true;
 747       case DMI_SBDATA3:
 748         sbdata[3] = value;
 749         return true;
 750       case DMI_AUTHDATA:
 751         D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value,
 752             challenge + secret));
 753         if (require_authentication) {
 754           if (value == challenge + secret) {
 755             dmstatus.authenticated = true;
 756           } else {
 757             dmstatus.authenticated = false;
 758             challenge = random();
 759           }
 760         }
 761         return true;
 762     }
 763   }
 764   return false;
 765 }
 766
 767 void debug_module_t::proc_reset(unsigned id)
 768 {
 769   havereset[id] = true;
 770   halted[id] = false;
 771 }