riscv/debug_module.cc

   1 #include <cassert>
   2
   3 #include "debug_module.h"
   4 #include "mmu.h"
   5
   6 #include "debug_rom/debug_rom.h"
   7
   8 debug_module_t::debug_module_t()
   9 {
  10   /* Copy Debug ROM into the page. */
  11   memcpy(raw_page + DEBUG_ROM_START - DEBUG_START,
  12       debug_rom_raw, debug_rom_raw_len);
  13 }
  14
  15 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
  16 {
  17   addr = DEBUG_START + addr;
  18
  19   fprintf(stderr, "ERROR: invalid load from debug module: %ld bytes at 0x%lx\n",
  20       len, addr);
  21   return false;
  22 }
  23
  24 bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
  25 {
  26   addr = DEBUG_START + addr;
  27
  28   if (addr & (len-1)) {
  29     fprintf(stderr, "ERROR: unaligned store to debug module: %ld bytes at 0x%lx\n",
  30         len, addr);
  31     return false;
  32   }
  33
  34   if (addr >= DEBUG_RAM_START && addr + len <= DEBUG_RAM_END) {
  35     memcpy(raw_page + addr - DEBUG_START, bytes, len);
  36     return true;
  37   } else if (len == 4 && addr == DEBUG_CLEARDEBINT) {
  38     clear_interrupt(bytes[4] | (bytes[5] << 8) |
  39         (bytes[6] << 16) | (bytes[7] << 24));
  40     return true;
  41   }
  42
  43   fprintf(stderr, "ERROR: invalid store to debug module: %ld bytes at 0x%lx\n",
  44       len, addr);
  45   return false;
  46 }
  47
  48 void debug_module_t::ram_write32(unsigned int index, uint32_t value)
  49 {
  50   char* base = raw_page + DEBUG_RAM_START - DEBUG_START + index * 4;
  51   base[0] = value & 0xff;
  52   base[1] = (value >> 8) & 0xff;
  53   base[2] = (value >> 16) & 0xff;
  54   base[3] = (value >> 24) & 0xff;
  55 }
  56
  57 char* debug_module_t::page(reg_t paddr)
  58 {
  59   fprintf(stderr, "dm::page(0x%lx)\n", paddr);
  60
  61   assert(PGSHIFT == 12);
  62
  63   if (paddr == (DEBUG_START & PGMASK)) {
  64     return raw_page;
  65   }
  66
  67   fprintf(stderr, "ERROR: invalid page to debug module at 0x%lx\n", paddr);
  68   return NULL;
  69 }