riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class debug_module_t : public abstract_device_t
  10 {
  11   public:
  12     bool load(reg_t addr, size_t len, uint8_t* bytes);
  13     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  14
  15     void ram_write32(unsigned int index, uint32_t value);
  16     uint32_t ram_read32(unsigned int index);
  17
  18     void set_interrupt(uint32_t hartid) {
  19       interrupt.insert(hartid);
  20     }
  21     void clear_interrupt(uint32_t hartid) {
  22       interrupt.erase(hartid);
  23     }
  24     bool get_interrupt(uint32_t hartid) const {
  25       return interrupt.find(hartid) != interrupt.end();
  26     }
  27
  28     void set_halt_notification(uint32_t hartid) {
  29       halt_notification.insert(hartid);
  30     }
  31     void clear_halt_notification(uint32_t hartid) {
  32       halt_notification.erase(hartid);
  33     }
  34     bool get_halt_notification(uint32_t hartid) const {
  35       return halt_notification.find(hartid) != halt_notification.end();
  36     }
  37
  38     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  39     // uses to access the DM.
  40     uint32_t dmi_read(unsigned address);
  41     void dmi_write(unsigned address, uint32_t value);
  42
  43   private:
  44     // Track which interrupts from module to debugger are set.
  45     std::set<uint32_t> interrupt;
  46     // Track which halt notifications from debugger to module are set.
  47     std::set<uint32_t> halt_notification;
  48     char debug_ram[DEBUG_RAM_SIZE];
  49 };
  50
  51 #endif