riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class sim_t;
  10
  11 typedef struct {
  12   bool haltreq;
  13   bool resumereq;
  14   unsigned hartsel;
  15   bool hartreset;
  16   bool dmactive;
  17   bool ndmreset;
  18 } dmcontrol_t;
  19
  20 typedef struct {
  21   bool allnonexistant;
  22   bool anynonexistant;
  23   bool allunavail;
  24   bool anyunavail;
  25   bool allrunning;
  26   bool anyrunning;
  27   bool allhalted;
  28   bool anyhalted;
  29   bool allresumeack;
  30   bool anyresumeack;
  31   bool authenticated;
  32   bool authbusy;
  33   bool cfgstrvalid;
  34   unsigned versionhi;
  35   unsigned versionlo;
  36 } dmstatus_t;
  37
  38 typedef enum cmderr {
  39     CMDERR_NONE = 0,
  40     CMDERR_BUSY = 1,
  41     CMDERR_NOTSUP = 2,
  42     CMDERR_EXCEPTION = 3,
  43     CMDERR_HALTRESUME = 4,
  44     CMDERR_OTHER = 7
  45 } cmderr_t;
  46
  47 typedef struct {
  48   bool busy;
  49   unsigned datacount;
  50   unsigned progsize;
  51   cmderr_t cmderr;
  52 } abstractcs_t;
  53
  54 typedef struct {
  55   unsigned autoexecprogbuf;
  56   unsigned autoexecdata;
  57 } abstractauto_t;
  58
  59 class debug_module_t : public abstract_device_t
  60 {
  61   public:
  62     debug_module_t(sim_t *sim);
  63
  64     void add_device(bus_t *bus);
  65
  66     bool load(reg_t addr, size_t len, uint8_t* bytes);
  67     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  68
  69     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  70     // uses to access the DM.
  71     // Return true for success, false for failure.
  72     bool dmi_read(unsigned address, uint32_t *value);
  73     bool dmi_write(unsigned address, uint32_t value);
  74
  75   private:
  76     static const unsigned progsize = 8;
  77
  78     sim_t *sim;
  79
  80     uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
  81     uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];
  82     uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE];
  83     uint8_t program_buffer[progsize * 4];
  84     uint8_t dmdata[DEBUG_DATA_SIZE];
  85
  86     bool halted[1024];
  87     bool resumeack[1024];
  88
  89     // Instruction that will be placed at the current hart's ROM entry address
  90     // after the current action has completed.
  91     uint32_t next_action;
  92     bool action_executed;
  93
  94     void write32(uint8_t *rom, unsigned int index, uint32_t value);
  95     uint32_t read32(uint8_t *rom, unsigned int index);
  96
  97     dmcontrol_t dmcontrol;
  98     dmstatus_t dmstatus;
  99     abstractcs_t abstractcs;
 100     abstractauto_t abstractauto;
 101     uint32_t command;
 102
 103     processor_t *current_proc() const;
 104     void reset();
 105     bool perform_abstract_command();
 106 };
 107
 108 #endif