Refactor how we track in-progress operations.
[riscv-isa-sim.git] / riscv / debug_module.h
1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
4
5 #include <set>
6
7 #include "devices.h"
8
9 class debug_module_t : public abstract_device_t
10 {
11 public:
12 debug_module_t();
13
14 bool load(reg_t addr, size_t len, uint8_t* bytes);
15 bool store(reg_t addr, size_t len, const uint8_t* bytes);
16 char* page(reg_t paddr);
17
18 void ram_write32(unsigned int index, uint32_t value);
19 uint32_t ram_read32(unsigned int index);
20
21 void set_interrupt(uint32_t hartid) {
22 fprintf(stderr, "set debug interrupt 0x%x\n", hartid);
23 interrupt.insert(hartid);
24 }
25 void clear_interrupt(uint32_t hartid) {
26 fprintf(stderr, "clear debug interrupt 0x%x\n", hartid);
27 interrupt.erase(hartid);
28 }
29 bool get_interrupt(uint32_t hartid) const {
30 return interrupt.find(hartid) != interrupt.end();
31 }
32
33 private:
34 // Track which interrupts from module to debugger are set.
35 std::set<uint32_t> interrupt;
36 // TODO: use PGSIZE, which requires solving some circular include dependencies.
37 char raw_page[4096];
38 };
39
40 #endif