riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class sim_t;
  10
  11 typedef struct {
  12   bool haltreq;
  13   bool resumereq;
  14   unsigned hartsel;
  15   bool hartreset;
  16   bool dmactive;
  17   bool ndmreset;
  18 } dmcontrol_t;
  19
  20 typedef struct {
  21   bool allnonexistant;
  22   bool anynonexistant;
  23   bool allunavail;
  24   bool anyunavail;
  25   bool allrunning;
  26   bool anyrunning;
  27   bool allhalted;
  28   bool anyhalted;
  29   bool authenticated;
  30   bool authbusy;
  31   bool cfgstrvalid;
  32   unsigned versionhi;
  33   unsigned versionlo;
  34 } dmstatus_t;
  35
  36 typedef struct {
  37   bool busy;
  38   unsigned datacount;
  39   unsigned progsize;
  40   enum {
  41     CMDERR_NONE = 0,
  42     CMDERR_BUSY = 1,
  43     CMDERR_NOTSUP = 2,
  44     CMDERR_EXCEPTION = 3,
  45     CMDERR_HALTRESUME = 4,
  46     CMDERR_OTHER = 7
  47   } cmderr;
  48 } abstractcs_t;
  49
  50 typedef struct {
  51   unsigned autoexecprogbuf;
  52   unsigned autoexecdata;
  53 } abstractauto_t;
  54
  55 class debug_module_data_t : public abstract_device_t
  56 {
  57   public:
  58     debug_module_data_t();
  59
  60     bool load(reg_t addr, size_t len, uint8_t* bytes);
  61     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  62
  63     uint32_t read32(reg_t addr) const;
  64     void write32(reg_t addr, uint32_t value);
  65
  66     uint8_t data[DEBUG_EXCHANGE_SIZE];
  67 };
  68
  69 class debug_module_t : public abstract_device_t
  70 {
  71   public:
  72     debug_module_t(sim_t *sim);
  73
  74     void add_device(bus_t *bus);
  75
  76     bool load(reg_t addr, size_t len, uint8_t* bytes);
  77     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  78
  79     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  80     // uses to access the DM.
  81     // Return true for success, false for failure.
  82     bool dmi_read(unsigned address, uint32_t *value);
  83     bool dmi_write(unsigned address, uint32_t value);
  84
  85   private:
  86     static const unsigned progsize = 8;
  87
  88     sim_t *sim;
  89
  90     uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
  91     uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];
  92     uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE];
  93     uint8_t program_buffer[progsize * 4];
  94     bool halted[1024];
  95     debug_module_data_t dmdata;
  96     // Instruction that will be placed at the current hart's ROM entry address
  97     // after the current action has completed.
  98     uint32_t next_action;
  99     bool action_executed;
 100
 101     void write32(uint8_t *rom, unsigned int index, uint32_t value);
 102     uint32_t read32(uint8_t *rom, unsigned int index);
 103
 104     dmcontrol_t dmcontrol;
 105     dmstatus_t dmstatus;
 106     abstractcs_t abstractcs;
 107     abstractauto_t abstractauto;
 108     uint32_t command;
 109
 110     processor_t *current_proc() const;
 111     void reset();
 112     bool perform_abstract_command();
 113 };
 114
 115 #endif