riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 2;
  31 const int RM_BITS = 3;
  32 const int BIGIMM_BITS = 20;
  33 const int BRANCH_ALIGN_BITS = 1;
  34 const int JUMP_ALIGN_BITS = 1;
  35
  36 #define SR_ET    0x0000000000000001ULL
  37 #define SR_EF    0x0000000000000002ULL
  38 #define SR_EV    0x0000000000000004ULL
  39 #define SR_EC    0x0000000000000008ULL
  40 #define SR_PS    0x0000000000000010ULL
  41 #define SR_S     0x0000000000000020ULL
  42 #define SR_UX    0x0000000000000040ULL
  43 #define SR_SX    0x0000000000000080ULL
  44 #define SR_IM    0x000000000000FF00ULL
  45 #define SR_VM    0x0000000000010000ULL
  46 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
  47 #define SR_IM_SHIFT 8
  48 #define IPI_IRQ 5
  49 #define TIMER_IRQ 7
  50
  51 #define CAUSE_EXCCODE 0x000000FF
  52 #define CAUSE_IP      0x0000FF00
  53 #define CAUSE_EXCCODE_SHIFT 0
  54 #define CAUSE_IP_SHIFT      8
  55
  56 #define FP_RD_NE  0
  57 #define FP_RD_0   1
  58 #define FP_RD_DN  2
  59 #define FP_RD_UP  3
  60 #define FP_RD_NMM 4
  61
  62 #define FSR_RD_SHIFT 5
  63 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  64
  65 #define FPEXC_NX 0x01
  66 #define FPEXC_UF 0x02
  67 #define FPEXC_OF 0x04
  68 #define FPEXC_DZ 0x08
  69 #define FPEXC_NV 0x10
  70
  71 #define FSR_AEXC_SHIFT 0
  72 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  73 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  74 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  75 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  76 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  77 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  78
  79 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  80
  81 // note: bit fields are in little-endian order
  82 struct itype_t
  83 {
  84   unsigned opcode : OPCODE_BITS;
  85   unsigned funct : FUNCT_BITS;
  86   signed imm12 : IMM_BITS;
  87   unsigned rs1 : XPRID_BITS;
  88   unsigned rd : XPRID_BITS;
  89 };
  90
  91 struct btype_t
  92 {
  93   unsigned opcode : OPCODE_BITS;
  94   unsigned funct : FUNCT_BITS;
  95   unsigned immlo : IMMLO_BITS;
  96   unsigned rs2 : XPRID_BITS;
  97   unsigned rs1 : XPRID_BITS;
  98   signed immhi : IMM_BITS-IMMLO_BITS;
  99 };
 100
 101 struct jtype_t
 102 {
 103   unsigned jump_opcode : OPCODE_BITS;
 104   signed target : TARGET_BITS;
 105 };
 106
 107 struct rtype_t
 108 {
 109   unsigned opcode : OPCODE_BITS;
 110   unsigned funct : FUNCT_BITS;
 111   unsigned functr : FUNCTR_BITS;
 112   unsigned rs2 : XPRID_BITS;
 113   unsigned rs1 : XPRID_BITS;
 114   unsigned rd : XPRID_BITS;
 115 };
 116
 117 struct ltype_t
 118 {
 119   unsigned opcode : OPCODE_BITS;
 120   unsigned bigimm : BIGIMM_BITS;
 121   unsigned rd : XPRID_BITS;
 122 };
 123
 124 struct ftype_t
 125 {
 126   unsigned opcode : OPCODE_BITS;
 127   unsigned ffunct : FFUNCT_BITS;
 128   unsigned rm : RM_BITS;
 129   unsigned rs3 : FPRID_BITS;
 130   unsigned rs2 : FPRID_BITS;
 131   unsigned rs1 : FPRID_BITS;
 132   unsigned rd  : FPRID_BITS;
 133 };
 134
 135 union insn_t
 136 {
 137   itype_t itype;
 138   jtype_t jtype;
 139   rtype_t rtype;
 140   btype_t btype;
 141   ltype_t ltype;
 142   ftype_t ftype;
 143   uint32_t bits;
 144 };
 145
 146 #include <stdio.h>
 147 class do_writeback
 148 {
 149 public:
 150   do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 151
 152   const do_writeback& operator = (reg_t rhs)
 153   {
 154 #if 0
 155     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 156 #endif
 157     rf[rd] = rhs;
 158     rf[0] = 0;
 159     return *this;
 160   }
 161
 162   operator reg_t() { return rf[rd]; }
 163
 164 private:
 165   reg_t* rf;
 166   int rd;
 167 };
 168
 169 #define throw_illegal_instruction \
 170   ({ if (utmode) throw trap_vector_illegal_instruction; \
 171      else throw trap_illegal_instruction; })
 172
 173 // helpful macros, etc
 174 #define RS1 XPR[insn.rtype.rs1]
 175 #define RS2 XPR[insn.rtype.rs2]
 176 #define RD do_writeback(XPR,insn.rtype.rd)
 177 #define RA do_writeback(XPR,1)
 178 #define FRS1 FPR[insn.ftype.rs1]
 179 #define FRS2 FPR[insn.ftype.rs2]
 180 #define FRS3 FPR[insn.ftype.rs3]
 181 #define FRD FPR[insn.ftype.rd]
 182 #define BIGIMM insn.ltype.bigimm
 183 #define SIMM insn.itype.imm12
 184 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 185 #define SHAMT (insn.itype.imm12 & 0x3F)
 186 #define SHAMTW (insn.itype.imm12 & 0x1F)
 187 #define TARGET insn.jtype.target
 188 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 189 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 190 #define RM ({ int rm = insn.ftype.rm; \
 191               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 192               if(rm > 4) throw_illegal_instruction; \
 193               rm; })
 194
 195 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 196 #define xpr64 (xprlen == 64)
 197 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
 198 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
 199 #define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 200 #define require_vector \
 201   ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
 202     else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
 203   })
 204 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 205 #define set_fp_exceptions ({ set_fsr(fsr | \
 206                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 207                              softfloat_exceptionFlags = 0; })
 208
 209 #define sext32(x) ((sreg_t)(int32_t)(x))
 210 #define zext32(x) ((reg_t)(uint32_t)(x))
 211 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 212 #define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
 213
 214 #ifndef RISCV_ENABLE_RVC
 215 # define set_pc(x) \
 216   do { if((x) & (sizeof(insn_t)-1)) \
 217        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 218        npc = (x); \
 219      } while(0)
 220 #else
 221 # define set_pc(x) \
 222   do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
 223        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 224        npc = (x); \
 225      } while(0)
 226 #endif
 227
 228 // RVC stuff
 229
 230 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 231 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
 232 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
 233
 234 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
 235 #define CRD do_writeback(XPR, CRD_REGNUM)
 236 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 237 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 238 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 239 #define CIMM5U ((insn.bits >> 5) & 0x1f)
 240 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 241 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 242 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 243 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 244
 245 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 246 #define rvc_rd_regmap rvc_rs1_regmap
 247 #define rvc_rs2b_regmap rvc_rs1_regmap
 248 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 249 #define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 250 #define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 251 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 252 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 253 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
 254 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 255
 256 // vector stuff
 257 #define VL vl
 258
 259 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 260 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 261 #define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
 262 #define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
 263 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 264 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 265 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 266 #define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
 267 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 268               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 269
 270 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 271 #define UT_LOOP_END }
 272 #define UT_LOOP_RS1 UT_RS1(i)
 273 #define UT_LOOP_RS2 UT_RS2(i)
 274 #define UT_LOOP_RD UT_RD(i)
 275 #define UT_LOOP_RA UT_RA(i)
 276 #define UT_LOOP_FRS1 UT_FRS1(i)
 277 #define UT_LOOP_FRS2 UT_FRS2(i)
 278 #define UT_LOOP_FRS3 UT_FRS3(i)
 279 #define UT_LOOP_FRD UT_FRD(i)
 280 #define UT_LOOP_RM UT_RM(i)
 281
 282 #define VEC_LOAD(dst, func, inc) \
 283   reg_t addr = RS1; \
 284   UT_LOOP_START \
 285     UT_LOOP_##dst = mmu.func(addr); \
 286     addr += inc; \
 287   UT_LOOP_END
 288
 289 #define VEC_STORE(src, func, inc) \
 290   reg_t addr = RS1; \
 291   UT_LOOP_START \
 292     mmu.func(addr, UT_LOOP_##src); \
 293     addr += inc; \
 294   UT_LOOP_END
 295
 296 enum vt_command_t
 297 {
 298   vt_command_stop,
 299 };
 300
 301 #endif